PXN20RM Datasheet, PDF (538/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Enhanced Direct Memory Access Controller (eDMA)
24.3.2.10 eDMA Clear Error Register (EDMA_CER)
The EDMA_CER provides a memory-mapped mechanism to clear a given bit in the EDMA_ERL to
disable the error condition flag for a given channel. The given value on a register write causes the
corresponding bit in the EDMA_ERL to be cleared. Setting bit 1 (CERR[0]) provides a global clear
function, forcing the entire contents of the EDMA_ERL to be zeroed, clearing all channel error indicators.
Reads of this register return all zeroes.
If bit 0 is set, the CERR command is ignored. This allows multiple byte registers to be written as a 32-bit
word. Reads of this register return all zeroes.
Offset: EDMA_BASE + 0x001D
R
W
Reset
0
1
2
3
4
5
NOP
CERR[0:6]
0
0
0
0
0
0
Figure 24-11. eDMA Clear Error Register (EDMA_CER)
Access: User write-only
6
7
0
0
Table 24-12. EDMA_CER Field Descriptions
Field
Description
NOP
CERR[0:6]
No operation.
0 Normal operation.
1 No operation, ignore bits 1–7.
Clear Error Indicator.
0–31 Clear corresponding bit in EDMA_ERL.
32–63 Reserved.
64–127 Clear all bits in EDMA_ERL.
Note: Bits 2 and 3 (CER[1:2]) are not used.
24.3.2.11 eDMA Set START Bit Register (EDMA_SSBR)
The EDMA_SSBR provides a memory-mapped mechanism to set the START bit in the TCD of the given
channel. The data value on a register write causes the START bit in the corresponding transfer control
descriptor to be set. Setting bit 1 (SSB[0]) provides a global set function, forcing all START bits to be set.
Reads of this register return all zeroes.
If bit 0 is set, the SSB command is ignored. This allows multiple byte registers to be written as a 32-bit
word. Reads of this register return all zeroes.
Offset: EDMA_BASE + 0x001E
R
W
Reset
0
1
2
3
4
5
NOP
SSB[0:6]
0
0
0
0
0
0
Figure 24-12. eDMA Set START Bit Register (EDMA_SSBR)
Access: User write-only
6
7
0
0
24-18
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor