PXN20RM Datasheet, PDF (223/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

System Integration Unit (SIU)
Offset: SIU_BASE + 0x09A8
Access: User read-only
1
1
2
0
1
2
3
2
2
2
2
2
2
2
2
2
2
2
4
5
6
7
8
9
10
11
12
13
14
15
R0
0
0 _{HLT HLT} 0
0
0
0
0
0
0
0
0
0
0
W
3
4
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
2
2
2
2
2
2
2
2
16
17
18
19
20
21
22
23
24
25
26
27
28
29 30
31
R0
0
0
0 _{HLT HLT HLT HLT} 0
0 _{HLT HLT HLT HLT} 0
0
W
20 21 22 23
26 27 28 29
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1 _{Reserved, do not write to this bit.}
2 _{Writes to this bit are reflected in the SIU_HLT1 and SIU_HLTACK1 register, but have no other effect.}
Figure 8-27. Halt Register 1 (SIU_HLT1)
Field
HLT3
HLT4
HLT20
HLT21
HLT22
HLT23
HLT26
HLT27
HLT28
HLT29
Table 8-28. SIU_HLT1 Register Field Descriptions
Description
Halt bit 3. Setting this bit halts the DMA module.
Halt bit 4. Setting this bit halts the NPC module.
Halt bit 20. Setting this bit halts the ESCI_M module.
Halt bit 21. Setting this bit halts the ESCI_L module.
Halt bit 22. Setting this bit halts the ESCI_K module.
Halt bit 23. Setting this bit halts the ESCI_J module.
Halt bit 26. Setting this bit halts the DSPI_D module.
Halt bit 27. Setting this bit halts the DSPI_C module.
Halt bit 28. Setting this bit halts the I²C_D module.
Halt bit 29. Setting this bit halts the I²C_C module.
8.3.2.24 Halt Acknowledge Register (SIU_HLTACKn)
The SIU_HLTACKn bits indicate that the peripheral requested to halt via the HLTn bit has completed its
halt process and has entered a halted state with the peripheral clocks disabled. The HLTACKn bits are
read-only; writes have no effect.
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
8-41