PXN20RM Datasheet, PDF (400/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

e200z0 Core (Z0)
— 1 cycle load latency
— Fully pipelined
— Big-endian support only
— Misaligned access support
— Zero load-to-use pipeline bubbles for aligned transfers
• Power management
— Low power design
— Power saving modes: doze, nap, sleep, and wait
— Dynamic power management of execution units
NOTE
The PXN20 does not use the core’s HID0[DOZE,NAP,SLEEP] bits to
enter/exit low-power modes. Entry to and exit from low-power modes is
managed by the CRP module.
14.2 Microarchitecture Summary
The execution pipeline four stages operate in an overlapped fashion, allowing single-clock instruction
execution for most instructions. These stages are as follows:
1. The instruction fetch
2. Instruction decode/register file read/effective address calculation
3. Execute/memory access
4. Register writeback
The integer execution unit consists of a 32-bit Arithmetic Unit (AU), a Logic Unit (LU), a 32-bit Barrel
shifter (Shifter), a Mask-Insertion Unit (MIU), a Condition Register manipulation Unit (CRU), a
Count-Leading-Zeros unit (CLZ), an 8x32 Hardware Multiplier array, result feed-forward hardware, and
a hardware divider.
Arithmetic and logical operations are executed in a single cycle with the exception of the divide and
multiply instructions. A count-leading-zeros unit operates in a single clock cycle.
The Instruction Unit contains a PC incrementer and a dedicated Branch Address adder to minimize delays
during change of flow operations. Sequential prefetching is performed to ensure a supply of instructions
into the execution pipeline. Prefetched instructions are placed into an instruction buffer with 2 entries, each
capable of holding a single 32-bit instruction or a pair of 16-bit instructions.
Conditional branches which are not taken execute in a single clock. All taken branches have an execution
time of two clocks.
Memory load and store operations are provided for byte, halfword, and word (32-bit) data with automatic
zero or sign extension of byte and halfword load data as well as optional byte reversal of data. These
instructions can be pipelined to allow effective single cycle throughput. Load and store multiple word
instructions allow low overhead context save and restore operations. The load/store unit contains a
14-2
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor