PXN20RM Datasheet, PDF (516/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

DMA Channel Multiplexer (DMA_MUX)
executions of the minor loop require a new start event be sent. This can either be a new software activation
or a transfer request from the DMA channel mux. The options for doing this are:
• Transfer all data in a single minor loop. By configuring the DMA to transfer all of the data in a
single minor loop (i.e.,major loop counter = 1), no re-activation of the channel is necessary. The
disadvantage to this option is the reduced granularity in determining the load that the DMA transfer
will incur on the system. For this option, the DMA channel should be disabled in the DMA channel
mux.
• Use explicit software re-activation. In this option, the DMA is configured to transfer the data using
both minor and major loops, but the processor is required to re-activate the channel (by writing to
the DMA registers) after every minor loop. For this option, the DMA channel should be disabled
in the DMA channel mux.
• Use an always enabled DMA source. In this option, the DMA is configured to transfer the data
using both minor and major loops, and the DMA channel mux does the channel re-activation. For
this option, the DMA channel should be enabled and pointing to an always enabled source. Note
that the re-activation of the channel can be continuous (DMA triggering is disabled) or can use the
DMA triggering capability. In this manner, it is possible to execute periodic transfers of packets of
data from one source to another without processor intervention.
23.5 Initialization/Application Information
23.5.1 Reset
The reset state of each individual bit is shown within the register description section (Section 23.3.2,
Register Descriptions). After reset, all channels are disabled and must be explicitly enabled before use.
23.5.2 Enabling and Configuring Sources
23.5.2.1 Enabling a Source with Periodic Triggering
1. Determine with which DMA channel the source will be associated. Only DMA channels 0–7 have
periodic triggering capability.
2. Clear the ENBL and TRIG bits of the DMA channel.
3. Ensure that the DMA channel is properly configured in the DMA. The DMA channel may be
enabled at this point.
4. In the PIT, configure the corresponding timer.
5. Select the source to be routed to the DMA channel. Write to the corresponding CHCONFIG
register, ensuring that the ENBL and TRIG bits are set.
Example 23-1. Configure DSPI_B Transmit for use with DMA Channel 2, with periodic triggering capability
1. Write 0x00 to CHCONFIG2 (base address + 0x02).
2. Configure channel 2 in the DMA, including enabling the channel.
3. Configure timer 3 in the periodic interrupt timer (PIT) for the desired trigger interval.
4. Write 0xD3 to CHCONFIG2 (base address + 0x02).
23-12
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor