PXN20RM Datasheet, PDF (1106/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Analog-to-Digital Converter (ADC)
Table 34-26. CTR2 Field Descriptions
Field
Description
INPLATCH
INPCMP
INPSAMP
Configuration bit for Latching phase duration.
0b Latching phase duration is one-half clock cycle.
1b Latching phase duration is one clock cycle.
Note: The 1b condition is possible only if INPCMP is bigger than 01b. Otherwise, it is automatically set to 0b
inside the ADC.
Configuration bits for the comparison duration. See Table 34-27.
Configuration bits for the sampling phase duration. See Table 34-28.
INPLATCH
0
0
1
1
1
1
1
1
Table 34-27. Max AD_clk Frequency and Related Configuration Settings
INPCMP
0b00 or 0b01
0b00 or 0b01
0b10
0b10
0b11
0b11
0b11
0b11
INPSAMPLE
0b0000 0011
0b0000 0100
0b0000 0100
0b0000 0101
0b0000 0110
0b0000 0111
0b0000 1000
0b0000 1001
AD_clk f_max
(MHz)
20
20 + 4%
20 + 4%
20 + 4%
32 + 4%
40 + 4%
50 + 4%
60 + 4%
AD_clk Phase Min Duration
High
Low
24
22.5
24
22.5
24
15
15
15
12
12
9
9
9
9
7.5
7.5
T_sample min
(ns)
125
168
168
135
132
128
134
128
INPLATCH
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Table 34-28. ADC Sampling and Conversion Timing
INPCMP
0b11
0b11
0b11
0b11
0b11
INPSAMP
0b0000 1001
0b0000 1010
0b0000 1011
0b0000 1100
0b0000 1101
T_sample1
8 * Tck
9 * Tck
10 * Tck
11 * Tck
12 * Tck
T_eval
30 * Tck
30 * Tck
30 * Tck
30 * Tck
30 * Tck
ndelay
1 * Tck
1 * Tck
1 * Tck
1 * Tck
1 * Tck
0b11
0b11
0b11
0b11
0b0000 1110
0b0000 1111
0b0001 0000
0b0001 0001
13 * Tck
14 * Tck
15 * Tck
16 * Tck
30 * Tck
30 * Tck
30 * Tck
30 * Tck
1 * Tck
1 * Tck
1 * Tck
1 * Tck
0b11
0b11
0b11
0b11
0b0001 0010
0b0001 0011
0b0001 0100
0b0001 0101
17 * Tck
18 * Tck
19 * Tck
20 * Tck
30 * Tck
30 * Tck
30 * Tck
30 * Tck
1 * Tck
1 * Tck
1 * Tck
1 * Tck
0b11
0b0001 0110
21 * Tck
30 * Tck
1 * Tck
T_conv
39 * Tck²
40 * Tck
41 * Tck
42 * Tck
43 * Tck
44 * Tck
45 * Tck
46 * Tck
47 * Tck
48 * Tck
49 * Tck
50 * Tck
51 * Tck
52 * Tck
34-26
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor