PXN20RM Datasheet, PDF (597/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Fast Ethernet Controller (FEC)
Table 25-30. FEC User Initialization (Before ECR[ETHER_EN])
Description
Initialize FRSR (optional)
Initialize EMRBR
Initialize ERDSR
Initialize ETDSR
Initialize (Empty) Transmit Descriptor ring
Initialize (Empty) Receive Descriptor ring
25.4.3 Microcontroller Initialization
In the FEC, the descriptor control RISC initializes some registers after ECR[ETHER_EN] is asserted.
After the microcontroller initialization sequence is complete, the hardware is ready for operation.
Table 25-31 shows microcontroller initialization operations.
Table 25-31. Microcontroller Initialization
Description
Initialize BackOff Random Number Seed
Activate Receiver
Activate Transmitter
Clear Transmit FIFO
Clear Receive FIFO
Initialize Transmit Ring Pointer
Initialize Receive Ring Pointer
Initialize FIFO Count Registers
25.4.4 User Initialization (After Asserting ECR[ETHER_EN])
After asserting ECR[ETHER_EN], the user can set up the buffer/frame descriptors and write to the TDAR
and RDAR. Refer to Section 25.5, Buffer Descriptors, for more details.
25.4.5 Network Interface Options
The FEC supports both an MII interface for 10/100 Mbps Ethernet and a 7-wire serial interface for 10
Mbps Ethernet. The interface mode is selected by the RCR[MII_MODE] bit. In MII mode
(RCR[MII_MODE] = 1), there are 18 signals defined by the IEEE 802.3 standard and supported by the
EMAC. These signals are shown in Table 25-32 below.
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
25-31