PXN20RM Datasheet, PDF (423/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Semaphores
processes/processors are locked out. Many software implementations include a spin-wait loop within the
lock function until the locking of the gate is accomplished. After the lock has been obtained, processor X
continues execution and updates the data values protected by the particular lock. After the updates are
complete, processor X unlocks (or opens) the software gate, allowing other processes/processors access to
the updated data values.
There are three important rules that must be followed for a correctly implemented system solution:
• All writes to shared data values or shared hardware resources must be protected by a gate variable.
• After a processor locks a gate, accesses to the shared data or resources by other
processes/processors must be blocked. This is enforced by software conventions.
• The processor that locks a particular gate is the only processor that can unlock, or open, that gate.
Information in the hardware gate identifying the locking processor can be useful for system-level
debugging.
The Hennessy/Patterson text on computer architecture offers this description of software gating:
“One of the major requirements of a shared-memory architecture multiprocessor is being able to
coordinate processes that are working on a common task. Typically, a programmer will use lock
variables to synchronize the processes.
The difficulty for the architect of a multiprocessor is to provide a mechanism to decide which
processor gets the lock and to provide the operation that locks a variable. Arbitration is easy for
shared-bus multiprocessors, since the bus is the only path to memory. The processor that gets the
bus locks out all the other processors from memory. If the CPU and bus provide an atomic swap
operation, programmers can create locks with the proper semantics. The adjective atomic is key,
for it means that a processor can both read a location and set it to the locked value in the same bus
operation, preventing any other processor from reading or writing memory.” [Hennessy/Patterson,
Computer Architecture: A Quantitative Approach, ppg. 471-472]
The classic text continues with a description of the steps required to lock/unlock a variable using an atomic
swap instruction.
“Assume that 0 means unlocked and 1 means locked. A processor first reads the lock variable to
test its state. A processor keeps reading and testing until the value indicates that the lock is
unlocked. The processor then races against all other processes that were similarly “spin waiting”
to see who can lock the variable first. All processes use a swap instruction that reads the old value
and stores a 1 into the lock variable. The single winner will see the 0, and the losers will see a 1
that was placed there by the winner. (The losers will continue to set the variable to the locked value,
but that doesn’t matter.) The winning processor executes the code after the lock and then stores a
0 into the lock when it exits, starting the race all over again. Testing the old value and then setting
to a new value is why the atomic swap instruction is called test and set in some instruction sets.”
[Hennessy/Patterson, Computer Architecture: A Quantitative Approach, ppg. 472-473]
The sole drawback to a hardware-based semaphore module is the limited number of semaphores versus
the infinite number that can be supported with Power Architecture reservation instructions.
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
15-11