PXN20RM Datasheet, PDF (867/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Enhanced Modular Input/Output Subsystem (eMIOS200)
EMIOS_CCNTR Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9
Output Pin
A1 Value
A2 Value
B1 Value
EDPOL = 0
Prescaler = 1
100%
Time
0%
0x000008 0x000007 0x000006 0x000005 0x000004 0x000003 0x000002 0x000001 0x000000
0x000007 0x000006 0x000005 0x000004 0x000003 0x000002 0x000001 0x000000
0x000008
Figure 28-43. OPWFMB Mode from 100% to 0% Duty Cycle
A 0% duty cycle signal is generated if A1 = 0 as shown in cycle 9 in Figure 28-43. In this case, the
B1 = 0x00_0008 match from cycle 8 occurs at the same time as the A1 = 0x00_0000 match from cycle 9.
Refer to Figure 28-40 for a description of the A1 and B1 match generation. In this case, the A1 match has
precedence over the B1 match and the output signal transitions to EDPOL.
28.4.1.1.13 Center-Aligned Output PWM Buffered with Dead-Time (OPWMCB) Mode
This operation mode generates a center-aligned PWM with dead-time insertion to the leading or trailing
edge. A1 and B1 registers are double buffered to allow smooth output signal generation when changing
A2 or B2 registers values.
The selected counter bus must be running in up/down counter mode, as shown in Figure 28-36. The time
base selected for a channel configured to OPWMCB mode should be a channel configured to MCB mode.
The BSL bits select the time base. The time base must start at 0x00_0001 and upward not prior to
OPWMCB mode is active. Register A1 contains the ideal duty cycle for the PWM signal and is compared
with the selected time base. Register B1 contains the dead-time value and is compared against the internal
counter. For a leading edge dead-time insertion, the output PWM duty cycle is equal to the difference
between register A1 and register B1, and for a trailing edge dead-time insertion, the output PWM duty
cycle is equal to the sum of register A1 and register B1. MODE[6] bit selects between trailing and leading
dead-time insertion, respectively.
NOTE
The internal prescaler of the OPWMCB channel must be set to the same
value of the MCB channel prescaler. These prescalers must also be
synchronized. In this case, A1 and B1 registers represent the same timing
scale for duty cycle and dead-time insertion.
Figure 28-44 shows the load of A1 and B1 registers, which occurs when the selected counter bus reaches
the value one. This counter value defines the cycle boundary. Values written to A2 or B2 within cycle (n)
are loaded into A1 or B1 registers, respectively, and used to generate matches in cycle (n + 1).
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
28-45