PXN20RM Datasheet, PDF (116/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Resets
4.3.2.8 Z0 Core Checkstop Reset
When the Z0 core enters a checkstop state, and the checkstop reset is enabled (SIU_SRCR[CRE1] bit), a
checkstop reset occurs. The internal reset signal and RESET pin are asserted. The SIU_RSR[CRS] bit is
set and all other reset status bits in the SIU_RSR are cleared.
4.3.2.9 JTAG Reset
A system reset occurs when JTAG is enabled and the EXTEST, CLAMP, or HIGHZ instruction is executed
by the JTAG controller. The internal reset signal is asserted. The state of the RESET pin is determined by
the JTAG instruction. The reset status bits in the SIU_RSR are unaffected by JTAG reset.
4.3.2.10 Software System Reset
A software system reset is caused by writing to the SIU_RCR[SSR] bit. Setting the SSR bit causes an
internal reset of the MCU. The internal reset signal and RESET pin are asserted. The SIU_RSR[SSRS] bit
is set, and all other reset status bits in the SIU_RSR are cleared.
4.4 Reset Configuration
The reset state of the system is:
• All pads on ports A–K are placed in a disabled mode with output enables, input enables, and pull
devices all disabled. PK9 is configured for BOOTCFG function.
• TDI pad is an input with pullup enabled.
• TDO pad is an output with fastest slew rate selected.
• TCK pad is an input with pulldown enabled.
• TMS pad is an input with pullup enabled.
• JCOMP pad is an input with pulldown enabled.
• RESET pin is configured as open drain output with pullup disabled and initially driven low, but
switched to an input with pullup enabled after the reset sequence.
• BOOTCFG pin is an input, the pin data is latched 4 clock cycles before the RESET signal is
negated (high).
• Nexus pads
— The following configuration is valid as long as the NPC is out of reset and enabled via JTAG:
– EVTO output with fastest slew rate enabled, high
– EVTI output buffer disabled, input buffer enabled, pullup enabled
– MCKO output with fastest slew rate enabled. Low until MCKO_EN = 1
– MDO[11:0] output with fastest slew rate enabled, low
– MSEO[1:0] output with fastest slew rate enabled, high
NOTE
Nexus is only available on the 256MAPBGA emulation package.
PXN20 Microcontroller Reference Manual, Rev. 1
4-4
Freescale Semiconductor