PXN20RM Datasheet, PDF (404/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

e200z0 Core (Z0)
SUPERVISOR Mode Program Model
General Registers
Condition Register
CR
Count Register
CTR SPR 9
General-Purpose
Registers
GPR0
GPR1
Exception Handling/Control Registers
SPR General
Save and Restore
Interrupt Vector Prefix
SPRG0 SPR 272
SRR0 SPR 26
IVPR SPR 63
SPRG1 SPR 273
SRR1 SPR 27
CSRR0 SPR 58
CSRR1 SPR 59
Link Register
LR
SPR 8
XER
XER
SPR 1
GPR31
DSRR0
DSRR1
SPR 574
SPR 575
Exception Syndrome
ESR
SPR 62
Machine Check
Syndrome Register
Processor Control Registers
Machine State
MSR
Processor Version
PVR _{SPR 287}
Processor ID
PIR
SPR 286
System Version¹
SVR SPR 1023
Hardware Implementation
Dependent¹
HID0 SPR 1008
HID1 SPR 1009
Debug Registers^{2 -}
Debug Control
DBCR0
SPR 308
DBCR1
SPR 309
DBCR2
SPR 310
Instruction Address
Compare
IAC1
SPR 312
IAC2
SPR 313
IAC3
SPR 314
IAC4
SPR 315
MCSR SPR 572
Data Exception Address
DEAR SPR 61
Memory Management Registers
Process ID
PID0 SPR 48
Configuration (Read-only
MMUCFG SPR 1015
Debug Status
DBSR SPR 304
Data Address Compare
DAC1
SPR 316
DAC2
SPR 317
Cache Registers
Cache Configuration
(Read-only)
1 - These e200-specific registers may not be
supported by other Power Architecture
processors
2 - Optional registers defined by the Power
Architecture Book E
3 - Read-only registers
L1CFG0 SPR 515
Figure 14-2. e200z0 Supervisor Mode Programmer’s Model
14-6
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor