PXN20RM Datasheet, PDF (593/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Fast Ethernet Controller (FEC)
Field
0–21
R_BOUND
30–31
Table 25-23. FRBR Field Descriptions
Descriptions
Reserved, read as 0 (except bit 21, which is read as 1).
Read-only. Highest valid FIFO RAM address.
Reserved, should be cleared.
25.3.4.21 FIFO Receive Start Register (FRSR)
The FRSR is a 32-bit register with one 8-bit field programmed by the user to indicate the starting address
of the receive FIFO. FRSR marks the boundary between the transmit and receive FIFOs. The transmit
FIFO uses addresses from the start of the FIFO to the location four bytes before the address programmed
into the FRSR. The receive FIFO uses addresses from FRSR to FRBR inclusive.
The FRSR register is initialized by hardware at reset. FRSR only needs to be written to change the default
value.
Offset: FEC_BASE + 0x0150
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R0
0
0
0
0
0
R_FSTART
0
0
W
Reset 0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
Figure 25-22. FIFO Receive Start Register (FRSR)
Table 25-24. FRSR Field Descriptions
Field
0–21
R_FSTART
30–31
Descriptions
Reserved, read as 0 (except bit 21, which is read as 1).
Address of first receive FIFO location. Acts as delimiter between receive and transmit FIFOs.
Reserved, read as 0.
25.3.4.22 Receive Descriptor Ring Start (ERDSR)
The ERDSR is written by the user. It provides a pointer to the start of the circular receive buffer descriptor
queue in external memory. This pointer must be 32-bit aligned; however, it is recommended it be made
128-bit aligned (evenly divisible by 16).
This register is not reset and must be initialized by the user prior to operation.
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
25-27