PXN20RM Datasheet, PDF (1207/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Nexus Development Interface (NDI)
NOTE
The OVC bits within the DC1 register can be set to delay the CPU in order
to alleviate (but not eliminate) potential overrun situations.
Error information is messaged out in the following format:
5
4
3
2
1
DATA
U-ADDR
DSZ
SRC
MSB 1–64 bits
1–32 bits
3 bits
4 bits
Max length = 109 bits; Min length = 15 bits
Figure 36-43. Error Message Format
TCODE (000110)
6 bits LSB
Data Trace Synchronization Messages
A data trace write/read with sync. message is messaged via the auxiliary port (provided data trace is
enabled) for the following conditions (see Table 36-35):
• Initial data trace message after exit from system reset or whenever data trace is enabled
• Upon returning from a CPU Low Power state.
• Upon exiting debug mode
• After occurrence of queue overrun (can be caused by any trace message), provided data trace is
enabled
• After the periodic data trace counter has expired indicating 255 without-sync data trace messages
have occurred since the last with-sync message occurred
• Upon assertion of the event in (EVTI) pin, the first data trace message is a synchronization message
if the EIC bits of the DC1 register have enabled this feature
• Upon data trace write/read after the previous DTM message was lost due to an attempted access to
a secure memory location
• Upon data trace write/read after the previous DTM message was lost due to a collision entering the
FIFO between the DTM message and any of the following: watchpoint message, ownership trace
message, or branch trace message
Data trace synchronization messages provide the full address (without leading zeros) and ensure that
development tools fully synchronize with data trace regularly. Synchronization messages provide a
reference address for subsequent data messages, in which only the unique portion of the data trace address
is transmitted. The format for data trace write/read with sync. messages is as follows:
5
4
3
2
1
DATA
F-ADDR
DSZ
SRC
TCODE (001101 or 001110)
MSB 1–64 bits
1–32 bits
3 bits
4 bits
6 bits
LSB
Max length = 109 bits; Min length = 15 bits
Figure 36-44. Data Write/Read with Sync. Message Format
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
36-57