PXN20RM Datasheet, PDF (374/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

e200z6 Core (Z6)
Figure 13-3. User Mode Programmer’s Model
13.2.1 Power Architecture Registers
The e200z6 core supports most of the registers defined by the Power Architecture embedded category.
Notable exceptions are the floating point registers FPR0–FPR31 and FPSCR. The e200z6 does not support
the Power Architecture floating point architecture in hardware. The supported Power Architecture
embedded category registers are described as follows:
13.2.1.1 User-Level Registers
The user-level registers can be accessed by all software with user or supervisor privileges. They include
the following:
• General-purpose registers (GPRs). The thirty-two 64-bit GPRs (GPR0–GPR31) serve as data
source or destination registers for integer and SPE APU instructions and provide data for
generating addresses. Power Architecture Book E instructions affect only the lower 32 bits of the
GPRs.
SPE APU instructions are provided which operate on the entire 64-bit register.
• Condition register (CR). The 32-bit CR consists of eight 4-bit fields, CR0–CR7, that reflect results
of certain arithmetic operations and provide a mechanism for testing and branching.
• The remaining user-level registers are SPRs. Note that the Power Architecture provides the mtspr
and mfspr instructions for accessing SPRs.
• Integer exception register (XER). The XER indicates overflow and carries for integer operations.
• Link register (LR). The LR provides the branch target address for the branch conditional to link
register (bclr, bclrl) instructions, and is used to hold the address of the instruction that follows a
branch and link instruction, typically used for linking to subroutines.
• Count register (CTR). The CTR holds a loop count that can be decremented during execution of
appropriately coded branch instructions. The CTR also provides the branch target address for the
branch conditional to count register (bcctr, bcctrl) instructions.
• The time-base facility (TB) consists of two 32-bit registers: time-base upper (TBU) and time-base
lower (TBL). These two registers are accessible in a read-only fashion to user-level software.
• SPRG–SPRG7. The Power Architecture Book E architecture defines software-use special purpose
registers (SPRGs). SPRG4–SPRG7 are accessible as read-only by user-level software. The e200z6
does not allow user mode access to the SPRG3 register (defined as implementation dependent by
Book E).
• USPRG0. The Power Architecture Book E architecture defines user software-use special purpose
register USPRG0 which is accessible in a read-write fashion by user-level software.
13.2.1.2 Supervisor-Level Only Registers
In addition to the registers accessible in user mode, supervisor-level software has access to additional
control and status registers an operating system used for configuration, exception handling, and other
operating system functions. The Power Architecture embedded category defines the following
supervisor-level registers:
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PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor