PXN20RM Datasheet, PDF (912/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Controller Area Network (FlexCAN)
29.4.1 Transmit Process
If the MB is active (transmission pending), write an ABORT code (‘1001’) to the code field of the control
and status word to request an abortion of the transmission, then read back the code field and the IFLAG1/2
register to check if the transmission was aborted (see Section 29.4.5.1, Transmission Abort Mechanism).
If backwards compatibility is desired (AEN in CANx_MCR negated), just write ‘1000’ to the Code field
to inactivate the MB but then the pending frame may be transmitted without notification (see
Section 29.4.5.2, Message Buffer Deactivation).
• Write the ID word.
• Write the data bytes.
• Write the length, control and code fields of the control and status word to activate the MB.
Once the MB is activated in the fourth step, it participates into the arbitration process and eventually is
transmitted according to its priority. At the end of the successful transmission, the value of the free-running
timer is written into the time stamp field, the code field in the control and status word is updated, a status
flag is set in the interrupt flag register and an interrupt is generated if allowed by the corresponding
interrupt mask register bit. The new code field after transmission depends on the code that was used to
activate the MB in step four (see Table 29-4 and Table 29-5 in Section 29.3.2, Message Buffer Structure).
When the abort feature is enabled (AEN in CANx_MCR is asserted), after the Interrupt Flag is asserted
for a MB configured as transmit buffer, the MB is blocked, therefore the CPU is not able to update it until
the interrupt flag be negated by CPU. It means that the CPU must clear the corresponding CANx_IFLAG
before starting to prepare this MB for a new transmission or reception.
29.4.2 Arbitration Process
This process selects which MB is transmitted next. All MBs programmed as transmit buffers are scanned
to find the lowest ID¹ or the lowest MB number or the highest priority, depending on the LBUF and
LPRIO_EN bits on the control register. The arbitration process is triggered in the following events:
• During the CRC field of the CAN frame
• During the error delimiter field of the CAN frame
• During intermission, if the winner MB defined in a previous arbitration was deactivated, or if there
was no MB to transmit, but the CPU wrote to the C/S word of any MB after the previous arbitration
finished
• When MBM is in idle or bus off state and the CPU writes to the C/S word of any MB
• Upon leaving freeze mode
When LBUF is asserted, the LPRIO_EN bit has no effect and the lowest number buffer is transmitted first.
When LBUF and LPRIO_EN are both negated, the MB with the lowest ID is transmitted first but. If LBUF
is negated and LPRIO_EN is asserted, the PRIO bits augment the ID used during the arbitration process.
With this extended ID concept, arbitration is done based on the full 32-bit ID and the PRIO bits define
which MB should be transmitted first, therefore MBs with PRIO = 000 have higher priority. If two or more
MBs have the same priority, the regular ID determines the priority of transmission. If two or more MBs
have the same priority (3 extra bits) and the same regular ID, the lowest MB is transmitted first.
1. If LBUF is negated, the arbitration considers not only the ID, but also the RTR and IDE bits placed inside the ID at the same
positions they are transmitted in the CAN frame.
29-28
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor