PXN20RM Datasheet, PDF (844/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Enhanced Modular Input/Output Subsystem (eMIOS200)
EMIOS_CCR/Mode
•••
Channel Controller
MODEn_en
•
••
MODE1_en
MODE0_en
Mode 0
Logic
Mode 1
Logic
•
••
Mode n
Logic
Control
Signals
Control Signals
Control Signals
••
•
••
Shared
Logic
Channel
Datapath
Figure 28-14. Unified Channel Control Block Diagram
28.4.1.1 Unified Channel Modes of Operation
The mode of operation of the unified channel is determined by the mode select bits MODE[0:6] in the
EMIOS_CCR[n] register (see Table 28-11 for details).
When entering an output mode (except for GPIO mode), the output flip-flop is set to the complement of
the EDPOL bit in the EMIOS_CCR[n] register.
As the internal counter EMIOS_CCNTR[n] continues to run in all modes (except for GPIO mode), it is
possible to use this as a time base if the resource is not used in the current mode.
28.4.1.1.1 General-Purpose Input/Output (GPIO) Mode
In GPIO mode, all input capture and output compare functions of the unified channel are disabled, the
internal counter (EMIOS_CCNTR[n] register) is cleared and disabled. All control bits remain accessible.
In order to prepare the unified channel for a new operation mode, writing to registers EMIOS_CADR[n]
or EMIOS_CBDR[n] stores the same value in registers A1/A2 or B1/B2, respectively.
The MODE[6] bit selects between input (MODE[6] = 0) and output (MODE[6] = 1) modes.
When changing the MODE bits, the application software must go to GPIO mode first to reset the unified
channel’s internal functions properly. Failure to do this could lead to invalid and unexpected output
compare or input capture results or the FLAGs being set incorrectly.
28-22
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor