PXN20RM Datasheet, PDF (875/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Enhanced Modular Input/Output Subsystem (eMIOS200)
MODE[6] = 1
Selected
Counter Bus
0x000008
0x000006
0x000004
0x000002
0x000001
Due to B1 Match
cycle n – 1
Output Pin
FLAG Set Event
Cycle n
Write to A2
Match A1
Cycle n+1
Match A1
Write to B2
Match B1
Match B1
Write to A2
Cycle n+2
Match B1
Time
Output Disable
A1 Value 0x000002
0x000004
0x000006
A2 Value 0x000002 0x000004
0x000006
B1 Value 0x000008
0x000006
B2 Value 0x000008
0x000006
EDPOL = 0
Figure 28-50. OPWMB Mode with Active Output Disable
Figure 28-51 shows a waveform changing from 100% to 0% duty cycle. In this case, EDPOL is 0. In this
example, B1 is programmed to the same value as the period of the external selected time base.
Selected Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9
Counter Bus
Output Pin
A1 Value
A2 Value
B1 Value
EDPOL = 0
Prescaler = 1
100%
0x000008
0x000007
0x000008
0x000007 0x000006
0x000006 0x000005
0x000005
0x000004
0x000004 0x000003
0x000003 0x000002
0x000002
0x000001
Time
0%
0x000001 0x000000
0x000000
Figure 28-51. OPWMB Mode from 100% to 0% Duty Cycle
In Figure 28-51, if B1 is set to a value lower than 0x00_0008, it is not possible to achieve 0% duty cycle
by changing only A1 register value. Because B1 matches have precedence over A1 matches the output pin
transitions to the opposite of EDPOL bit at B1 match. If B1 is set to 0x00_0009, for instance, B1 match
does not occur, thus a 0% duty cycle signal is generated.
28.4.1.1.15 Output Pulse Width Modulation with Trigger (OPWMT) Mode
OPWMT mode (MODE[0:6] = 010_0110) is intended to support the generation of Pulse Width
Modulation signals where the period is not modified while the signal is being output, but where the duty
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
28-53