PXN20RM Datasheet, PDF (278/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Interrupts and Interrupt Controller (INTC)
Table 10-2. INTC_MCR Field Descriptions (continued)
Field
Description
VTES_PRC0
For software mode only, the Vector Table Entry Size for Processor 0 (Z6). The VTES_PRC0 bit controls the
number of 0s to the right of INTVEC_PRC0 in INTC_IACKR_PRC0. If the contents of INTC_IACKR_PRC0
are used as an address of an entry in a vector table, then the number of rightmost 0s will determine the size
of each vector table entry.
0 4 bytes.
1 8 bytes.
HVEN_PRC0
Hardware Vector Enable for Processor 0 (Z6). The HVEN bit controls whether the INTC is in hardware vector
mode or software vector mode. Refer to Section 10.1.3, Modes of Operation, for details of handshaking with
the processor in each mode.
0 Software vector mode.
1 Hardware vector mode.
10.3.2.2 INTC Current Priority Register for Processor 0 (Z6) (INTC_CPR_PRC0)
Offset: INTC_BASE_ADDR + 0x0008
0
1
2
3
4
5
6
7
R0 0
0
0000
0
W
Reset 0 0
0
0000
0
Access: User read/write
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19 20 21 22
23
24
25
26
27
28
29
30
31
R0 0
0
0000
0
0
0
0
0
PRI
W
Reset 0 0
0
0000
0
0
0
0
0
1
1
1
1
Figure 10-10. INTC Current Priority Register for Processor 0 (Z6) (INTC_CPR_PRC0)
Table 10-3. INTC_CPR_PRC0 Field Descriptions
Field
PRI
Description
Priority. PRI is the priority of the currently executing Z6 ISR according to the field values defined in Table 10-4.
The current priority register masks any peripheral or software settable interrupt request at the same or
lower priority of the current value than the PRI field in INTC_CPR_PRC0 from generating an interrupt
request to processor 0 (Z6). When INTC_IACKR_PRC0 is read in software vector mode, or the interrupt
acknowledge signal from the processor is asserted in hardware vector mode, the value of PRI is pushed
onto the LIFO, and PRI is updated with the priority of the preempting interrupt request. When
INTC_EOIR_PRC0 is written, the LIFO is popped into the INTC_CPR_PRC0’s PRI field. An exception
case in hardware vector mode to this behavior is described in Section 10.1.3.2, Hardware Vector Mode.
The masking priority can be raised or lowered by writing to the PRI field, supporting the PCP. Refer to
Section 10.5.5, Priority Ceiling Protocol.
10-10
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor