PXN20RM Datasheet, PDF (938/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Deserial – Serial Peripheral Interface (DSPI)
Table 30-5. DSPI_CTARn Field Description (continued)
Field
Description
CPHA
LSBFE
PCSSCK
Clock Phase. The CPHA bit selects which edge of SCK causes data to change and which edge causes data to
be captured. This bit is used in both master and slave mode. For successful communication between serial
devices, the devices must have identical clock phase settings. Continuous SCK is only supported for
CPHA = 1.
0 Data is captured on the leading edge of SCK and changed on the following edge.
1 Data is changed on the leading edge of SCK and captured on the following edge.
LSB First. The LSBFE bit selects if the LSB or MSB of the frame is transferred first. This bit is only used in master
mode. When operating in TSB configuration, this bit should be always 1.
0 Data is transferred MSB first.
1 Data is transferred LSB first.
PCS to SCK Delay Prescaler. The PCSSCK field selects the prescaler value for the delay between assertion of
PCS and the first edge of the SCK. This field is only used in master mode. The table below lists the prescaler
values. See the CSSCK[0:3] field description for details on how to compute the PCS to SCK delay.
PCSSCK
00
01
10
11
PCS to SCK Delay Prescaler Value
1
3
5
7
PASC
After SCK Delay Prescaler. The PASC field selects the prescaler value for the delay between the last edge of
SCK and the negation of PCS. This field is only used in master mode. The table below lists the prescaler values.
See the ASC[0:3] field description for details on how to compute the After SCK Delay.
PASC
00
01
10
11
After SCK Delay Prescaler Value
1
3
5
7
PDT Delay after Transfer Prescaler. The PDT field selects the prescaler value for the delay between the negation of
the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame. The PDT field
is only used in master mode. The table below lists the prescaler values. See the DT[0:3] field description for
details on how to compute the delay after transfer.
PDT
00
01
10
11
Delay after Transfer Prescaler Value
1
3
5
7
30-12
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor