PXN20RM Datasheet, PDF (343/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Flash Memory Array and Control
Table 12-10. ADR Field Descriptions
Field
Description
SAD
Shadow Address. The SAD bit qualifies the address captured during an ECC Event Error, Single Bit Correction,
or State Machine operation.
The SAD register is not writable.
0 Address Captured is from Main Array Space.
1 Address Captured is from Shadow Array Space.
ADDR[20:3]
Address. The ADR register provides the first failing address in the event of ECC event error (MCR[EER] set),
single bit correction (MCR[SBC] set), as well as providing the address of a failure that may have occurred in a
state machine operation (MCR[PEG] cleared). ECC event errors take priority over single bit corrections, which
take priority over state machine errors. This is especially valuable in the event of a RWW operation, where the
read senses an ECC error or single bit correction, and the state machine fails simultaneously. This address is
always a Double Word address that selects 64 bits.
The ADR register is writable, and can be used in the UTest ECC Logic Check. If the ECC logic check is enabled
(UT0[EIE] = 1) then the ADR register will not update for ECC event error, single bit correction, or state machine
errors.
If MCR[EER] or MCR[SBC] are set, the ADR register is locked from writing. MCR[PEG] does not affect the
writability of the ADR register.
12.3.2.8 Platform Flash Configuration Register for Port n (PFCRPn)
The PFLASH configuration register for port 0 (PFCRP0) is used to specify operation of port p0 of the flash
memory module. This register also has two bits (ARB and PRI) to control arbitration between the p0/p1
ports.
The PFLASH configuration register for port 1 (PFCRP1) is used to specify operation of port p1 of the flash
memory module.
The PFCRPn register is shown in Figure 12-10 and Table 12-11.
Offset: FLASH_REGS_BASE + 0x001C (PFCRP0)
FLASH_REGS_BASE + 0x0020 (PFCRP1)
Access: User read/write
0
R
W
Reset¹ 0
123
4
5
LBCFG
ARB PRI
0 —² —² —³ —³
6
7
8
9
10
11
12
13
14
15
0
0
0
M8PFE
M6PFE M5PFE M4PFE
M2PFE M1PFE M0PFE
0
0
0
0
0
0
0
0
0
0
16 17 18
R
APC
W
19 20
WWSC
21
22
23
RWSC
24
25
26
27
28
0
DPF
EN
0
0
IPFEN
29
30
PFLIM
31
BFEN
Reset 1 1 1 1 1
1
1
1
0
0
0
0
0
0
0
0
1 _{Reset value for PFCRP0 = 0x0800_FF00, PFCRP1 = 0x3000_FF00.}
2 _{Reset value for port 0 is LBCFG = 0b0000, port 1 is LBCFG = 0b0011.}
3 _{ARB and PRI are only available in PFCRP0. ARB is reset to 1 and PRI is reset to 0. For PFCRP1, ARB and PRI}
are both reserved, with a reset value of 0.
Figure 12-10. Platform Flash Configuration Register for Port n (PFCRPn)
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
12-17