PXN20RM Datasheet, PDF (506/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

DMA Channel Multiplexer (DMA_MUX)
23.1.2 Features
The DMA_MUX has these major features:
• 32 independently selectable DMA channel routers
— Four channels with normal or periodic triggering capability
— 24 channels with normal operation only
— Each channel router can be assigned to 1 of 55 possible peripheral DMA sources, eight always
enabled sources, or one always disabled source.
23.1.3 Modes of Operation
DMA channels 0–7 may be used in the following modes, but channels 8–31 may only be configured to
disabled or normal mode.
• Disabled mode
In this mode, the DMA channel is disabled. Because disabling and enabling of DMA channels is
done primarily via the DMA registers, this mode is used mainly as the reset state for a DMA
channel in the DMA channel mux. It may also be used to temporarily suspend a DMA channel
while reconfiguration of the system takes place (changing the period of a DMA trigger, for
example).
• Normal mode
In this mode, a DMA source (such as SCI transmit or SCI receive for example) is routed directly
to the specified DMA channel. The operation of the DMA_MUX in this mode is completely
transparent to the system.
• Periodic trigger mode
In this mode, a DMA source may only request a DMA transfer (such as when a transmit buffer
becomes empty or a receive buffer becomes full) periodically. Configuration of the period is done
in the registers of the periodic interrupt timer.
23.2 External Signal Description
The DMA_MUX has no external signals.
23.3 Memory Map and Registers
This section provides a detailed description of all DMA_MUX registers.
23.3.1 Module Memory Map
The DMA_MUX memory map is shown in Table 23-1. The address of each register is given as an offset
to the DMA_MUX base address. Registers are listed in address order, identified by complete name and
mnemonic, and list the type of accesses allowed.
All registers are accessible via 8-bit, 16-bit, or 32-bit accesses. However, 16-bit accesses must be aligned
to 16-bit boundaries and 32-bit accesses must be aligned to 32-bit boundaries. As an example,
23-2
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor