PXN20RM Datasheet, PDF (786/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Media Local Bus (MLB)
Table 27-12. VCCR Field Descriptions
Field
Description
UMA
[7:0]
UMI
[7:0]
MMA
[7:0]
MMI
[7:0]
User Major Revision. For first release of the PXN20, the value is 0x03.
User Minor Revision. For first release of the PXN20, the value is 0x00.
MLB Device Major Revision. For first release of the PXN20, the value is 0x02.
MLB Device Minor Revision.For first release of the PXN20, the value is 0x02.
27.3.2.6 Synchronous Base Address Configuration Register (SBCR)
The Synchronous Base Address Configuration Register (SBCR) allows system software to define the base
address for synchronous RX/TX system memory buffers.
Offset: MLB_BASE + 0x0020
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
SRBA[31:16]
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
STBA[31:16]
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 27-7. Synchronous Base Address Configuration Register (SBCR)
Table 27-13. SSBCR Field Descriptions
Field
Description
SRBA Synchronous Receive Base Address. This base address is shared by all synchronous RX channels and defines the
[31:16] upper 16 bits of the 32-bit system memory address for these channels.
STBA Synchronous Transmit Base Address. This base address is shared by all synchronous TX channels and defines the
[31:16] upper 16 bits of the 32-bit system memory address for these channels.
27.3.2.7 Asynchronous Base Address Configuration Register (ABCR)
The Asynchronous Base Address Configuration Register (ABCR) allows system software to define the
base address for asynchronous RX/TX system memory buffers.
27-14
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor