PXN20RM Datasheet, PDF (338/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Flash Memory Array and Control
Table 12-5. LML Field Descriptions (continued)
Field
Description
MLOCK[1:0]
Mid Address Space Block Lock. A value of 1 in a bit of the lock register signifies that the corresponding block
is locked for program and erase. A value of 0 in the lock register signifies that the corresponding block is
available to receive program and erase pulses. The block numbering for Mid Address Space starts with
MLOCK[0] and continues until all blocks are accounted.
The lock register is not writable once an interlock write is completed until MCR[DONE] is set at the completion
of the requested operation. Likewise, the lock register is not writable if a high voltage operation is suspended.
MLOCK is also not writeable during UTest operations, when AIE is high.
Upon reset, information from the shadow block is loaded into the block registers. The LOCK bits may be
written as a register. Reset causes the bits to go back to their shadow block value. The default value of the
LOCK bits (assuming erased shadow location) is locked.
In the event that blocks are not present (due to configuration or total memory size), the LOCK bits default to
be locked, and are not writable. The reset value is always 1 (independent of the shadow block), and register
writes have no effect.
LLOCK[9:0]
MLOCK is not writable unless LME is high.
Low Address Space Block Lock. A value of 1 in a bit of the lock register signifies that the corresponding block
is locked for program and erase. A value of 0 in the lock register signifies that the corresponding block is
available to receive program and erase pulses. The block numbering for Low Address Space starts with
LLOCK[0] and continues until all blocks are accounted.
For more details on LLOCK, please see MLOCK bit description.
LLOCK is not writable unless LME is high.
12.3.2.3 High Address Space Block Locking Register (HBL)
The High Address Space Block Locking Register (HBL) provides a means to protect blocks from being
modified.
NOTE
A reset value of 1* in Figure 12-5 indicates that the reset value of these
registers is determined by Flash values in the shadow block. An erased
shadow block causes the reset value to be 1.
The HBL register is shown in Figure 12-5 and Table 12-6.
12-12
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor