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PXN20RM Datasheet, PDF (46/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller | |||
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Introduction
1.4 PXN21 Block Diagram
Figure 1-2 shows a top-level block diagram for the PXN21.
PXN21 Block Diagram
Debug
JTAG
Nexus3 (Z6)
Nexus2+ (Z0)
e200z0 Core
VLE
Masters
e200z650 Core
VLE
MMU (32 TLB)
FPU/SPE
32 KB Cache
4/8 Way
32 kHz
XTAL
128 kHz
IRC
4â40 MHz
XTAL
FMPLL
Semaphores
32-ch DMA
Mux
16 MHz
IRC
Crossbar Switch (XBAR)
Memory Protection Unit (MPU)
VREG
Controller
RTC/API
SWT
STM
INTC
PIT
BAM
SIU
2 MB
Flash
(ECC)
ECSM
PBRIDGE B
8 x UART/LIN
2 x I2C
64 x ADC
2 x SPI
32 x eMIOS
5 x CAN
CTU
PBRIDGE A
4 x UART/LIN
2 x SPI
2 x I2C
128 KB
SRAM
(ECC)
Standby RAM
ECSM
ADC
BAM
CAN
CTU
ECC
ECSM
eDMA
eMIOS
FMPLL
I2C
INTC
JTAG
â Analog-to-digital converter
â Boot assist module
â Controller area network controller
â Cross triggering unit
â Error correction code
â Error correction status module
â Enhanced direct memory access controller
â Timed input/output
â Frequency-modulated phase-locked loop
â Inter-integrated circuit controller
â Interrupt controller
â Joint Test Action Group interface
MPU
â Memory protection unit
NDI
â Nexus debug interface
PBRIDGE â Peripheral I/O bridge
PIT
â Periodic interrupt timer
RTC
â Real time clock
SIU
â System integration unit
SPI
â Serial peripheral interface controller
STM
â System timer module
SWT
â Software watchdog timer
UART/LIN â Universal asynchronous receiver/transmitter/
local interconnect network
VREG â Voltage regulator
Figure 1-2. PXN21 Block Diagram
PXN20 Microcontroller Reference Manual, Rev. 1
1-4
Freescale Semiconductor
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