PXN20RM Datasheet, PDF (543/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Enhanced Direct Memory Access Controller (eDMA)
A channel’s ability to preempt another channel can be disabled by setting EDMA_CPR[DPA]. When a
channel’s preempt ability is disabled, that channel cannot suspend a lower priority channel’s data transfer;
regardless of the lower priority channel’s ECP setting. This allows for a pool of low priority, large data
moving channels to be defined. These low priority channels can be configured to not preempt each other,
thus preventing a low priority channel from consuming the preempt slot normally available a true, high
priority channel.
Offset: EDMA_BASE + 0x0100 + n
Access: User read/write
0
1
2
3
4
5
6
7
R
ECP
DPA
W
GRPPRI
CHPRI
Reset
0
0
0
0
—¹
1 _{The reset value for the channel priority field, CHPRI[0–3], is equal to the corresponding channel number for each priority}
register; that is, EDMA_CPRI0[CHPRI] = 0b0000 and EDMA_CPR15[CHPRI] = 0b1111.
Figure 24-17. eDMA Channel n Priority Register (EDMA_CPRn)
Table 24-18. EDMA_CPRn Field Descriptions
Field
Description
ECP
Enable Channel Preemption.
0 Channel n cannot be suspended by a higher priority channel’s service request.
1 Channel n can be temporarily suspended by the service request of a higher priority channel.
DPA
Disable preempt ability.
0 Channel n can suspend a lower priority channel.
1 Channel n cannot suspend any channel, regardless of channel priority.
GRPPRI[0:1] Channel n current group priority. Group priority assigned to this channel group when fixed-priority arbitration
is enabled. These two bits are read-only; writes are ignored. The reset value for the group priority fields is equal
to the corresponding channel number for each priority register; that is, EDMA_CPR31[GRPPRI] = 0b01.
CHPRI[0:3]
Channel n Arbitration Priority. Channel priority when fixed-priority arbitration is enabled. The reset value for the
channel priority fields CHPRI[0–3], is equal to the corresponding channel number for each priority register; that
is, EDMA_CPR31[CHPRI] = 0b1111.
24.3.2.17 Transfer Control Descriptor (TCD)
Each channel requires a 32-byte transfer control descriptor for defining the desired data movement
operation. The channel descriptors are stored in the local memory in sequential order: channel 0, channel
1,... channel 31. The definitions of the TCD are presented as eight 32-bit values. Table 24-19 is a field list
of the basic TCD structure.
Table 24-19. TCDn 32-bit Memory Structure
eDMA Offset
TCDn Field
0x1000+(32 x n)+0x0000
0x1000+(32 x n)+0x0004
0x1000+(32 x n)+0x0008
Source address (saddr)
Transfer attributes
Signed source address offset (soff)
Inner minor byte count (nbytes)
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
24-23