PXN20RM Datasheet, PDF (900/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Controller Area Network (FlexCAN)
Table 29-8. CANx_CTRL Field Descriptions
Bits
Description
CLK_SRC
CAN Engine Clock Source. Selects the clock source to the CAN Protocol Interface (CPI) to be either the system
clock (driven by the PLL) or the crystal oscillator clock. The selected clock is the one fed to the prescaler to
generate the serial clock (SCK). In order to guarantee reliable operation, this bit should only be changed while
the module is disabled.
0 The CAN engine clock source is the oscillator clock.
1 The CAN engine clock source is the system clock.
LPB
Loop Back. Configures FlexCAN to operate in loop-back mode. See Section 29.4.8, Modes of Operation
Details, for information about this operating mode.
0 Loop back disabled.
1 Loop back enabled.
TWRN_MSK
This bit provides a mask for the Tx Warning Interrupt associated with the TWRN_INT flag in the ESR register.
This bit has no effect if the WRN_EN bit in CANx_MCR is negated and it is read as zero when WRN_EN is
negated.
1 Tx Warning Interrupt enabled.
0 Tx Warning Interrupt disabled.
RWRN_MSK
This bit provides a mask for the RX Warning Interrupt associated with the RWRN_INT flag in the Error and
Status Register. This bit has no effect if the WRN_EN bit in CANx_MCR is negated and it is read as zero when
WRN_EN is negated.
1 Rx Warning Interrupt enabled.
0 Rx Warning Interrupt disabled.
SMP
Sampling Mode. Defines the sampling mode of each bit in the receiving messages (Rx).
0 Just one sample is used to determine the Rx bit value.
1 Three samples are used to determine the value of the received bit: the regular one (sample point) and 2
preceding samples, a majority rule is used.
BOFF_REC
Bus Off Recovery Mode. Defines how FlexCAN recovers from bus off state. If this bit is negated, automatic
recovering from bus off state occurs according to the CAN Specification 2.0B. If this bit is set, automatic
recovering from bus off is disabled and the module remains in bus off state until the bit is negated by the user.
If the negation occurs before 128 sequences of 11 recessive bits are detected on the CAN bus, then bus off
recovery happens as if the BOFF_REC bit had never been asserted. If the negation occurs after 128 sequences
of 11 recessive bits occurred, then FlexCAN re-synchronizes to the bus by waiting for 11 recessive bits before
joining the bus. After negation, the BOFF_REC bit can be re-asserted again during bus off, but it is only effective
the next time the module enters bus off. If BOFF_REC was negated when the module entered bus off, asserting
it during bus off is not effective for the current bus off recovery.
0 Automatic recovering from bus off state enabled, according to CAN Spec 2.0 part B.
1 Automatic recovering from bus off state disabled.
TSYN
Timer Sync Mode. Enables a mechanism that resets the free-running timer each time a message is received
in message buffer 0. This feature provides means to synchronize multiple FlexCAN stations with a special
SYNC message (that is, global network time). If the FEN bit in CANx_MCR is set (FIFO enabled), MB8 is used
for timer synchronization instead of MB0.
0 Timer sync feature disabled.
1 Timer sync feature enabled.
Note: There is a possibility of 4–5 ticks count skew between the different FlexCAN stations that would operate
in this mode.
LBUF
Lowest Buffer Transmitted First. This bit defines the ordering mechanism for message buffer
transmission.When asserted, the LPRIO_EN bit does not affect the priority arbitration.
0 Buffer with highest priority is transmitted first.
1 Lowest number buffer is transmitted first.
29-16
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor