PXN20RM Datasheet, PDF (394/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

e200z6 Core (Z6)
Table 13-12. Interrupts and Conditions (continued)
Interrupt
Interrupt Type Vector Offset
Register
Enables¹
Core Register
in Which
State
Information is
Saved
Causing Conditions
Machine check IVOR 1
Data storage
IVOR 2
Instruction
storage
External input
Alignment
IVOR 3
IVOR 4²
IVOR 5
Program
IVOR 6
Floating-point
unavailable
System call
AP unavailable
Decrementer
IVOR 7
IVOR 8
IVOR 9
IVOR 10
Fixed interval
timer
IVOR 11
Watchdog
timer
IVOR 12
Data TLB error
Instruction TLB
error
IVOR 13
IVOR 14
ME
—
—
EE, src
—
—
—
—
—
EE, DIE
EE, FIE
CE, WIE
—
—
CSSR[0:1]
SRR[0:1]
SRR[0:1]
SRR[0:1]
SRR[0:1]
SRR[0:1]
SRR[0:1]
SRR[0:1]
SRR[0:1]
SRR[0:1]
SRR[0:1]
CSRR[0:1]
SRR[0:1]
SRR[0:1]
• Machine check exception and MSR[ME] = 1
• ISI, ITLB error on first instruction fetch for an exception
handler
• Parity error signaled on cache access
• Write bus error on buffered store or cache line push
• Access control
• Byte ordering due to misaligned access across page
boundary to pages with mismatched E bits
• Cache locking exception
• Precise external termination error
• Access control.
• Precise external termination error.
External interrupt is asserted and MSR[EE] = 1
• lmw, stmw not word aligned
• lwarx or stwcx. not word aligned
• dcbz with disabled cache or no cache present, or to W or I
storage
• SPE ld and st instructions not properly aligned
Illegal, privileged, trap, FP enabled, AP enabled,
unimplemented operation
MSR[FP] = 0 and attempt to execute a Book E floating point
operation
Execution of the system call (sc) instruction
Unused by e200z6
Decrementer timeout, and as specified in Book E: Enhanced
PowerPC^TMArchitecture, Rev 1.0, Ch. 8, pg. 194–195 and in
the e200z6 PowerPC^tm Core Reference Manual, Rev 0.
Fixed-interval timer timeout and as specified in Book E:
Enhanced PowerPC^TMArchitecture, Rev 1.0, Ch. 8, pg.
195–196 and in the e200z6 PowerPC^tm Core Reference
Manual, Rev 0.
Watchdog timeout: as specified in Book E: Enhanced
PowerPC^TMArchitecture, Rev 1.0, Ch. 8, pg. 196–197 and in
the e200z6 PowerPC^TM Core Reference Manual, Rev 0.
Data translation lookup did not match a valid entry in the TLB
Instruction translation lookup did not match a valid TLB entry
13-30
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor