PXN20RM Datasheet, PDF (403/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

e200z0 Core (Z0)
• Run-time access to the processor memory map via the JTAG port. This allows for enhanced
download/upload capabilities.
• Watchpoint messaging through the auxiliary interface.
• Watchpoint trigger enable of program trace messaging.
• Auxiliary interface for higher data input/output (Nexus interface shared with Z6 core).
— 12 message data out pins (MDO[11:0])
— Two message start/end out pins (MSEO[1:0])
— One watchpoint event pin (EVTO)
— One event in pin (EVTI)
— One message clock out (MCKO) pin
• Registers for program trace, ownership trace, and watchpoint trigger control.
• All features controllable and configurable via the JTAG port.
14.3 Core Registers and Programmer’s Model
This section describes the registers implemented in the e200z0 core. It includes an overview of registers
defined by the Power Architecture Book E architecture, highlighting differences in how these registers are
implemented in the e200 core, and provides a detailed description of e200-specific registers. Full
descriptions of the architecture-defined register set are provided in Power Architecture Book E
Specification.
The Power Architecture Book E defines register-to-register operations for all computational instructions.
Source data for these instructions are accessed from the on-chip registers or are provided as immediate
values embedded in the opcode. The three-register instruction format allows specification of a target
register distinct from the two source registers, thus preserving the original data for use by other
instructions. Data is transferred between memory and registers with explicit load and store instructions
only.
Figure 14-2 and Figure 14-3 show the e200 register set including the registers which are accessible while
in supervisor mode, and the registers which are accessible in user mode. The number to the right of the
special-purpose registers (SPRs) is the decimal number used in the instruction syntax to access the register
(for example, the integer exception register (XER) is SPR 1).
NOTE
e200z0 is a 32-bit implementation of the Power Architecture Book E
specification. In this document, register bits are sometimes numbered from
bit 0 (Most Significant Bit) to 31 (Least Significant Bit), rather than the
Book E numbering scheme of 32:63, thus register bit numbers for some
registers in Book E are 32 higher.
Where appropriate, the Book E defined bit numbers are shown in
parentheses.
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
14-5