PXN20RM Datasheet, PDF (1004/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Enhanced Serial Communication Interface (eSCI)
Field
LRES
WU
WUD
PRTY
LIN
RXIE
TXIE
WUIE
STIE
PBIE
CIE
CKIE
FCIE
Table 31-9. eSCI_LCR1 Field Descriptions
Description
LIN FSM Resync. This bit controls the state of the LIN protocol engine.
0 LIN protocol engine in normal mode.
1 LIN protocol engine hold in initial state.
LIN Bus Wake-Up Trigger. This bit is used to trigger the generation of a wake-up signal on the LIN bus, as
described in Section 31.4.6.6, LIN Wakeup.
0 Write has no effect.
1 Write triggers the generation of a wakeup signal.
LIN Bus Wake-Up Delimiter Time. This field determines how long the LIN protocol engine waits after the end of
the transmitted wakeup signal, before starting the next LIN frame transmission.
00 4 bit times.
01 8 bit times.
10 32 bit times.
11 64 bit times.
Parity Generation Control. This bit controls the generation of the two parity bits in the LIN header.
0 Parity bits generation disabled.
1 Parity bits generation enabled.
LIN Mode Control. This bit controls whether the device is in SCI or LIN Mode.
0 SCI Mode.
1 LIN Mode.
Receive Data Ready Interrupt Enable. This bit controls the eSCI_IFSR2[RXRDY] interrupt request generation.
0 RXRDY interrupt request generation disabled.
1 RXRDY interrupt request generation enabled.
Transmit Data Ready Interrupt Enable. This bit controls the eSCI_IFSR2[TXRDY] interrupt request generation.
0 TXRDY interrupt request generation disabled.
1 TXRDY interrupt request generation enabled.
LIN Wakeup Received Interrupt Enable. This bit controls the eSCI_IFSR2[LWAKE] interrupt request generation.
0 LWAKE interrupt request generation disabled.
1 LWAKE interrupt request generation enabled.
Slave Timeout Flag Interrupt Enable. This bit controls the eSCI_IFSR2[STO] interrupt request generation.
0 STO interrupt request generation disabled.
1 STO interrupt request generation enabled.
Physical Bus Error Interrupt Enable. This bit controls the eSCI_IFSR2[PBERR] interrupt request generation.
0 PBERR interrupt request generation disabled.
1 PBERR interrupt request generation enabled.
CRC Error Interrupt Enable. This bit controls the eSCI_IFSR2[CERR] interrupt request generation.
0 CERR interrupt request generation disabled.
1 CERR interrupt request generation enabled.
Checksum Error Interrupt Enable. This bit controls the eSCI_IFSR2[CKERR] interrupt request generation.
0 CKERR interrupt request generation disabled.
1 CKERR interrupt request generation enabled.
Frame Complete Interrupt Enable. This bit controls the eSCI_IFSR2[FRC] interrupt request generation.
0 FRC interrupt request generation disabled.
1 FRC interrupt request generation enabled.
31-14
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor