PXN20RM Datasheet, PDF (362/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Flash Memory Array and Control
5. Set the UT0[AIE] bit.
If desired, the Array Integrity operation may be aborted prior to UT0[AID] going high. This may
be done by clearing the UT0[AIE] bit and then continuing to the next step. It should be noted that
in the event of an aborted array integrity check the MISR registers will contain a signature for the
portion of the operation that was completed prior to the abort, and will not be deterministic. Prior
to doing another array integrity operation, the UM0, UM1, UM2 and UM3 registers may need to
be initialized to the desired seed value by doing register writes.
6. Wait until the UT0[AID] bit goes high.
7. Read values in the MISR registers (UM0 through UM4) to ensure correct signature.
8. Write a logic 0 to the UT0[AIE] bit.
12.4.2.2 Factory Margin Read
Factory margin read must be done following “Initial Factory Conditions” (see note 2 in Table A-1). One
factory margin read is allowed per erase.
Factory margin read may be done to selected and unlocked blocks by combining UT0[MRE] and
UT0[MRV] with the array integrity check. If UT0[MRE] is set, UT0[AIS] has no effect, and the reads will
be done sequentially.
The data to be read is customer-specific. Thus, a customer can provide user code into the flash and the
correct MISR value is calculated. The customer is free to provide any random or non-random code, and a
valid MISR signature is calculated. Once the operation is completed, the result of the reads can be checked
by reading the MISR value. Factory margin read is a self-timed event, and is independent of system clocks
or wait states selected. Margin ECC corrections or detections are not done during the factory margin read
test.
1. Enable UTest mode.
2. Select the block, or blocks to be receive margin read check by writing ones to the appropriate
registers in LMS or HBS/EHS registers. Make sure that selected blocks are also unlocked.
NOTE
It is not possible to do UTest operations on the shadow block.
NOTE
It is possible to do User Mode array reads during the factory margin read
test, if desired, but the partition rules for Read While Write used during
program and erase are in effect during factory margin reads.
3. Set the UT0[MRE] bit.
4. Set the UT0[MRV] bit to the desired value to perform One’s margin or Zero’s margin.
5. Seed the MISR fields in UM0 through UM4 with the desired values.
6. Set the UT0[AIE] bit.
If desired, the margin read operation may be aborted prior to UT0[AID] going high. This may be
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PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor