PXN20RM Datasheet, PDF (410/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

e200z0 Core (Z0)
Table 14-3. Exceptions and Conditions (continued)
Interrupt Type
Interrupt Vector
Offset Register
Causing Conditions
AP unavailable
IVOR 9
Unused
Decrementer
IVOR 10
Unused
Fixed Interval
Timer
IVOR 11
Unused
Watchdog Timer
IVOR 12
Unused
Data TLB Error
IVOR 13
Unused
Instruction TLB
Error
IVOR 14
Unused
Debug
IVOR 15
Trap, Instruction Address Compare, Data Address Compare, Instruction
Complete, Branch Taken, Return from Interrupt, Interrupt Taken, External
Debug Event, Unconditional Debug Event
Reserved
IVOR 16-31
—
1 _{Autovectored External and Critical Input interrupts use this IVOR. Vectored interrupts supply an interrupt vector offset directly.}
Table 14-4 summarizes the e200z0 interrupts. Each ISR begins at a fixed offset as defined below.
Table 14-4. e200z0 Interrupts
IRQ # Offset Size [Byte]
Resource
— 0x0000
— 0x0010
— 0x0020
— 0x0030
— 0x0040
— 0x0050
— 0x0060
— 0x0070
— 0x0080
— 0x0090
— 0x00F0
— 0x0100
16
16
16
16
16
16
16
16
16
96
16
1792
Critical Input (NMI)
Machine check
Data Storage
Instruction Storage
External Input (INTC software vector mode)
Alignment
Program
Reserved
System call
Unused
Debug
Unused
14-12
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor