PXN20RM Datasheet, PDF (1105/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Analog-to-Digital Converter (ADC)
Address: ADC_BASE + 0x0098
Access: User read/write
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R _INP 0
W ^LATCH
0
0
0
INPCMP
0
INPSAMP
Reset 0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
1
Figure 34-25. Conversion Timing Register 1 (CTR1)
Table 34-25. CTR1 Field Descriptions
Field
Description
INPLATCH
INPCMP
INPSAMP
Configuration bit for Latching phase duration.
0b Latching phase duration is one-half clock cycle.
1b Latching phase duration is one clock cycle.
Note: The 1b condition is possible only if INPCMP is bigger than 01b. Otherwise, it is automatically set to 0b
inside the ADC.
Configuration bits for the comparison duration.See Table 34-27.
Configuration bits for the sampling phase duration. See Table 34-28.
34.3.2.25 Conversion Timing Register 2 (CTR2)
Conversion Timing Register 2 (CTR2) is associated with group 2 channels (channels 64–95).
Address: ADC_BASE + 0x009C
Access: User read/write
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R _INP 0
w
0
W ^LATCH
0
INPCMP
0
INPSAMP
Reset 0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
1
Figure 34-26. Conversion Timing Register 2 (CTR2)
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
34-25