PXN20RM Datasheet, PDF (358/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Flash Memory Array and Control
12.4.1.3.1 Software Locking
A software mechanism is provided to independently lock/unlock each high-, mid-, and low-address space
against program and erase.
Software locking is done through the LML (low-/mid-address space block locking register), SLL
(secondary low-/mid-address space block locking register), or HBL (high-address space block locking
register). These can be written through register writes and read through register reads.
When the program/erase operations are enabled through hardware, software locks are enforced through
doing register writes.
12.4.1.3.2 Flash Program Suspend/Resume
The program sequence may be suspended to allow read access to the flash core. It is not possible to erase
or program during a program suspend. Interlock writes should not be attempted during program suspend.
A program suspend can be initiated by changing the value of the MCR[PSUS] bit from a 0 to a 1.
MCR[PSUS] can be set high at any time when MCR[PGM] and MCR[EHV] are high. A 0 to 1 transition
of MCR[PSUS] causes the flash module to start the sequence to enter program suspend, which is a read
state. The module is not suspended until MCR[DONE] = 1. At this time flash core reads may be attempted.
After it is suspended, the flash core may be read only. Reads to the blocks being programmed/erased return
indeterminate data.
The program sequence is resumed by writing a logic 0 to MCR[PSUS]. MCR[EHV] must be set to a 1
before clearing MCR[PSUS] to resume operation. When the operation resumes, the flash module
continues the program sequence from one of a set of predefined points. This may extend the time required
for the program operation.
12.4.1.4 Flash Erase
Erase changes the value stored in all bits of the selected blocks to logic 1. Locked or disabled blocks cannot
be erased. If multiple blocks are selected for erase during an erase sequence, the blocks are erased
sequentially starting with the lowest numbered block and terminating with the highest. Aborting an erase
operation leaves the flash core blocks being erased in an indeterminate data state. This can be recovered
by executing an erase on the affected blocks.
The erase sequence consists of the following sequence of events:
1. Change the value in the MCR[ERS] bit from 0 to a 1.
2. Select the block, or blocks, to be erased by writing 1s to the appropriate registers in LMS or HBS.
If the shadow row is to be erased, this step may be skipped, and LMS and HBS are ignored. For
shadow row erase, see section Section 12.4.3, Flash Shadow Block, for more information.
NOTE
Lock and select are independent. If a block is selected and locked, no erase
can occur. See Section 12.3.2.2, Low/Mid Address Space Block Locking
Register (LML), Section 12.3.2.3, High Address Space Block Locking
Register (HBL), and Section 12.3.2.4, Secondary Low/Mid Address Space
Block Locking Register (SLL), for more information.
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PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor