PXN20RM Datasheet, PDF (354/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Flash Memory Array and Control
• The read state is active when PGM = 1 or ERS = 1 in the MCR and high-voltage operation is
ongoing (read-while-write).
NOTE
Reads done to the partition(s) being operated on (either erased or
programmed) result in an error and the RWE bit in the MCR is set.
• The read state is active when PGM = 1 and PSUS = 1 in the MCR (program suspend).
• The read state is active when ERS = 1 and ESUS = 1 and PGM = 0 in the MCR (erase suspend).
NOTE
FC reads are done through the BIU. In many cases the BIU will do page
buffering to allow sequential reads to be done with higher performance. This
can create a data coherency issue that must be handled with software. Data
coherency can be an issue after a program, erase, or shadow row operations.
In flash user mode, registers can be written. Array can be written to do interlock writes.
Reads attempted to invalid locations result in indeterminate data. Invalid locations occur when addressing
is done to blocks that do not exist in non 2ⁿ array sizes.
Interlock writes attempted to invalid locations (due to blocks that do not exist in non 2ⁿ array sizes) will
result in an interlock occurring, but attempts to program or erase these blocks will not occur since they are
forced to be locked.
12.4.1.2 Read While Write (RWW)
The flash core is divided into partitions. Partitions are always comprised of two or more blocks. Partitions
are used to determine read-while-write (RWW) groupings. While a write (program or erase) is being done
within a given partition, a read can be simultaneously executed to any other partition. Partitions are listed
in Table 12-1. Each partition in high address space comprises of two 256 KB blocks. The shadow block
has unique RWW restrictions described in Section 12.4.3, Flash Shadow Block.
The FC is also divided into blocks to implement independent erase or program protection. The shadow
block exists outside the normal address space and is programmed, erased, and read independently of the
other blocks. The shadow block is included to support systems that require NVM for security or system
initialization information.
A software mechanism is provided to independently lock or unlock each block in high-, mid-, and
low-address space against program and erase. Two hardware locks are also provided to enable/disable the
FC for program/erase. See Section 12.4.1.3.1, Software Locking, for more information.
12.4.1.3 Flash Programming
Programming changes the value stored in an array bit from logic 1 to logic 0 only. Programming cannot
change a stored logic 0 to a logic 1. Addresses in locked/disabled blocks cannot be programmed. The user
can program the values in any or all of four words within a page in a single program sequence. Word
addresses are selected using bits 3:2 of the page-bound word.
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PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor