PXN20RM Datasheet, PDF (984/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Deserial – Serial Peripheral Interface (DSPI)
DSPI_RSER is asserted. The RFDF_DIRS bit in the DSPI_RSER selects whether a DMA request or an
interrupt request is generated.
30.4.12.6 Receive FIFO Overflow Interrupt Request
The receive FIFO overflow request indicates that an overflow condition in the RX FIFO has occurred. A
receive FIFO overflow request is generated when RX FIFO and shift register are full and a transfer is
initiated. The RFOF_RE bit in the DSPI_RSER must be set for the interrupt request to be generated.
Depending on the state of the ROOE bit in the DSPI_MCR, the data from the transfer that generated the
overflow is either ignored or shifted in to the shift register. If the ROOE bit is set, the incoming data is
shifted in to the shift register. If the ROOE bit is negated, the incoming data is ignored.
30.4.12.7 DMA Requests
The connection of the DSPI DMA request signals to the DMA channel mux is described in Table 23-4.
30.4.12.8 Interrupt Requests
The DSPI interrupts are connected as described in Table 23-4.
30.4.13 Power Saving Features
The DSPI supports three power-saving strategies:
• Halt mode
• Module disable mode—clock gating of non-memory mapped logic
• Clock gating of slave interface signals and clock to memory-mapped logic
30.4.13.1 Halt Mode
By setting the appropriate bit in the SIU_HLT0 register, a request is made to shut down all clocks in the
DSPI. If no serial transfer is in progress, the DSPI immediately asserts an acknowledge signal to the
system, allowing the clocks to be disabled. If a serial transfer is in progress when the request is received,
the DSPI waits until it reaches a frame boundary before it asserts the acknowledge signal to the system.
The status of this acknowledge signal can be determined by reading the SIU_HLTACK0 register.
While the clocks are shut off, the DSPI memory-mapped logic is not accessible. The states of the interrupt
and DMA request signals cannot be changed while in halt mode.
Halt mode is exited by negating the appropriate bit in the SIU_HLT0 register.
30.4.13.2 Module Disable Mode
Module disable mode is a block-specific mode that the DSPI can enter to save power. Host software can
initiate the module disable mode by writing a 1 to the MDIS bit in the DSPI_MCR.
When the MDIS bit is asserted, the DSPI negates ipg_enable_clk at the next frame boundary. If
implemented, the ipg_enable_clk signal can stop the clock to the non-memory mapped logic. When
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PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor