PXN20RM Datasheet, PDF (337/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Flash Memory Array and Control
Offset: FLASH_REGS_BASE + 0x0004
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R LME 0
0
0
0
0
0
0
0
0
0
0
0
SLOCK
W
MLOCK
Reset 0
0
0
0
0
0
0
0
0
0
0
1*
0
0
1*
1*
16
R0
W
Reset 0
Field
LME
SLOCK
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
LLOCK
0
0
0
0
0
1* 1* 1* 1* 1*
1*
1* 1*
1*
1*
Figure 12-4. Low/Mid Address Block Locking Register (LML)
Table 12-5. LML Field Descriptions
Description
Low/Mid Address Lock Enable. This bit is used to enable the Lock registers (SLOCK, MLOCK and LLOCK)
to be set or cleared by register writes. This bit is a status bit only, and may not be written or cleared, and the
reset value is 0. The method to set this bit is to write a password, and if the password matches, the LME bit
is set to reflect the status of enabled, and is enabled until a reset operation occurs. For LME, the password
0xA1A1_1111 must be written to the LML register.
0 Low/Mid Address Locks are disabled, and cannot be modified.
1 Low/Mid Address Locks are enabled to be written.
Shadow Lock. This bit is used to lock the shadow block from programs and erases. The SLOCK register is
not writable once an interlock write is completed until MCR[DONE] is set at the completion of the requested
operation. Likewise, SLOCK register is not writable if a high voltage operation is suspended. SLOCK is also
not writeable during UTest operations, when AIE is high.
Upon reset, information from the shadow block is loaded into the SLOCK register. The SLOCK bit may be
written as a register. Reset causes the bits to go back to their shadow block value. The default value of the
SLOCK bits (assuming erased shadow location) is locked. SLOCK is not writable unless LME is high.
0 The shadow block can receive program and erase pulses.
1 The shadow block is locked for program and erase.
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
12-11