PXN20RM Datasheet, PDF (800/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Media Local Bus (MLB)
serial format required by the MLB interface. Data is transferred over the MLB in quadlets (32-bit words).
The MLB protocol supports as many as 32 quadlets per frame.
27.4.1 Clocking Requirements
The system clock (SYS_CLK) requirements for operation are shown in Table 27-23.
Table 27-23. Minimum MediaLB System Clock Requirements
Fs
44.1 kHz
48.0 kHz
48.1 kHz
MLBCLK
256 FS
512 FS
1024 FS
256 FS
512 FS
1024 FS
256 FS
512 FS
1024 FS
Minimum System Clock Speed
12 MHz
23 MHz
46 MHz
13 MHz
25 MHz
50 MHz
13 MHz
25 MHz
50 MHz
27.4.1.1 Reset
Soft reset of the physical and logical channel blocks is provided via the DDCE[MRS] bit.
Hard reset of the physical and logical channel blocks is enabled via the DCCR[MHRE] bit. When set,
reception of the global or device system reset commands resets the physical and link layers.
27.4.2 Interrupts
The MLB module generates 18 different interrupts, which are summarized in Table 27-24. For more
information on interrupts, please seeChapter 10, Interrupts and Interrupt Controller (INTC).
Table 27-24. MLB Interrupts
Interrupt Name
MLB Channel Interrupt
MLB System Interrupt
MLB Logical Channel 0 Interrupt
MLB Logical Channel 1 Interrupt
MLB Logical Channel 2 Interrupt
MLB Logical Channel 3 Interrupt
PXN20
Interrupt Vector
Interrupt Flag Bits
Interrupt Mask Bits
95
CSCR0[20:31]
CECR0[9:15]
to
to
CSCR15[20:31]
CECR15[9:15]
96
SSCR[25:31]
SMCR[25:31]
97
CSCR0[20:31]
CECR0[9:15]
98
CSCR1[20:31]
CECR1[9:15]
99
CSCR2[20:31]
CECR2[9:15]
100
CSCR3[20:31]
CECR3[9:15]
27-28
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor