PXN20RM Datasheet, PDF (562/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Enhanced Direct Memory Access Controller (eDMA)
e) read_byte(0x1008), read_byte(0x1009), read_byte(0x100a), read_byte(0x100b)
f) write_word(0x2008)  third iteration of the minor loop
g) read_byte(0x100c), read_byte(0x100d), read_byte(0x100e), read_byte(0x100f)
h) write_word(0x200c)  last iteration of the minor loop
6. eDMA engine writes: TCD.SADDR = 0x1010, TCD.DADDR = 0x2010, TCD.CITER = 1.
7. eDMA engine writes: TCD.ACTIVE = 0.
8. The channel retires  one iteration of the major loop.
The eDMA goes idle or services the next channel.
9. Second hardware (eDMA peripheral request) requests channel service.
10. The channel is selected by arbitration for servicing.
11. eDMA engine writes: TCD.DONE = 0, TCD.START = 0, TCD.ACTIVE = 1.
12. eDMA engine reads: channel TCD data from local memory to internal register file.
13. The source to destination transfers are executed as follows:
a) read_byte(0x1010), read_byte(0x1011), read_byte(0x1012), read_byte(0x1013)
b) write_word(0x2010)  first iteration of the minor loop
c) read_byte(0x1014), read_byte(0x1015), read_byte(0x1016), read_byte(0x1017)
d) write_word(0x2014)  second iteration of the minor loop
e) read_byte(0x1018), read_byte(0x1019), read_byte(0x101a), read_byte(0x101b)
f) write_word(0x2018)  third iteration of the minor loop
g) read_byte(0x101c), read_byte(0x101d), read_byte(0x101e), read_byte(0x101f)
h) write_word(0x201c)  last iteration of the minor loop  major loop complete
14. eDMA engine writes: TCD.SADDR = 0x1000, TCD.DADDR = 0x2000, TCD.CITER = 2
(TCD.BITER).
15. eDMA engine writes: TCD.ACTIVE = 0, TCD.DONE = 1, EDMA_IRQRn = 1.
16. The channel retires  major loop complete.
The eDMA goes idle or services the next channel.
24.5.5.3 Modulo Feature
The modulo feature of the eDMA provides the ability to implement a circular data queue in which the size
of the queue is a power of two. MOD is a 5-bit bitfield for both the source and destination in the TCD and
specifies which lower address bits are allowed to increment from their original value after the
address + offset calculation. All upper address bits remain the same as in the original value. A setting of 0
for this field disables the modulo feature.
Table 24-23 shows how the transfer addresses are specified based on the setting of the MOD field. Here a
circular buffer is created where the address wraps to the original value while the 28 upper address bits
(0x1234567x) retain their original value. In this example the source address is set to 0x12345670, the
offset is set to 4 bytes and the mod field is set to 4, allowing for a 2⁴ byte (16-byte) size queue.
24-42
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor