PXN20RM Datasheet, PDF (137/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Offset from
CRP_BASE
(0xFFFE_C000)
0x0070
0x0074–0x03FF
Table 6-1. CRP Memory Map (continued)
Clocks, Reset, and Power (CRP)
Register
CRP_SOCSC—SoC status and control register
Reserved
Access Reset Value Section/Page
R/W 0x4000_0000 6.2.2.12/6-15
6.2.2 Register Descriptions
This section lists the CRP registers in address order and describes the registers and their bit fields.
6.2.2.1 Clock Source Register (CRP_CLKSRC)
The CRP_CLKSRC contains:
• Enable bits for the 32 kHz OSC, 128 kHz IRC, and 4 – 40 MHz OSC
• Low power configuration for the 4 – 40 MHz OSC
• The trim values for the 16 MHz IRC and 128 kHz IRC
Offset: CRP_BASE + 0x0000
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R IRC 0 0 0 0
W ^TRIM
EN
PREDIV
0
0
0
0 _{EN128K EN32 ENLP EN40M}
IRC KOSC OSC OSC
Reset¹ 0
0
0
0
0
0
0
0
0
00 0
0
0
0
1
16
17
18
19
20
21
22
23
24
25 26 27
28
29
30
31
R0 0 0
W
TRIM128IRC
00
TRIM16IRC
Reset¹ 0
0
0
1
1
1
1
1
0
01 1
1
1
1
1
1 _{These bits are only reset by power-on, VDD12 LVI, VDD33 LVI, VDDSYN LVI, VDD5 Low LVI, and VDD5 LVI.}
Figure 6-2. Clock Source Register (CRP_CLKSRC)
Table 6-2. CRP_CLKSRC Field Descriptions
Field
IRCTRIMEN
PREDIV
Description
IRC Trim Enable. The IRCTRIMEN bit enable write access to TRIM128IRC and TRIM16IRC.
0 IRC trim bit writes disabled.
1 IRC trim bit writes enabled.
RTC Clock Pre-divider. The PREDIV bits control the pre-divider for the RTC clock source. Divide clock
sources are the 32 kHz OSC, 128 kHz IRC, 16 MHz IRC, or the 4 – 40 MHz OSC. See the CLKSEL bitfield
in Table 6-3.The pre-divider is in addition to any other divide selects internal to the RTC logic.
000 Divide by 1
001 Divide by 2
010 Divide by 4
011 Divide by 8
100 Divide by 16
Other Reserved
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor
6-5