PXN20RM Datasheet, PDF (469/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Error Correction Status Module (ECSM)
Table 19-6. EEGR Field Descriptions (continued)
Field
Description
PREI_SEL Platform RAM Error Injection Select. Platform RAM Error Injection Select. The platform contains two platform RAM
blocks with ECC. This bit selects which RAM is injected.
0 PRAM0 is injected.
1 PRAM1 is injected.
ERRBIT
Error Bit Position. The vector defines the bit position, which is complemented to create the data inversion on the
write operation. For the creation of 2-bit data inversions, the bit specified by this field plus the odd parity bit of the
ECC code are inverted.
The platform RAM controller follows a vector bit ordering scheme where LSB = 0. Errors in the ECC syndrome bits
can be generated by setting this field to a value greater than the RAM width. For example, consider a 32-bit RAM
implementation.
The 32-bit ECC approach requires seven code bits for a 32-bit word. For PRAM data width of 32 bits, the actual
SRAM (32b data + 7b for ECC = 39 bits. The following association between the ERRBIT field and the corrupted
memory bit is defined:
if ERRBIT = 0, then RAM[0] is inverted
if ERRBIT = 1, then RAM[1] is inverted
...
if ERRBIT = 31, then RAM[31] is inverted
if ERRBIT = 64,then ECC Parity[0] is inverted
if ERRBIT = 65,then ECC Parity[1] is inverted
...
if ERRBIT = 70,then ECC Parity[6] is inverted
Note: For ERRBIT values of 32 to 63 and greater than 70, no bit position is inverted.
NOTE
If an attempt to force a non-correctable inversion by asserting
EEGR[FRCNCI] or EEGR[FRC1NCI], and EEGR[ERRBIT] equals 64, no
data inversion is generated.
The only allowable values for the 4 control bit enables {FR11BI, FRC1BI,
FRCNCI, FR1NCI} are {0,0,0,0}, {1,0,0,0}, {0,1,0,0}, {0,0,1,0} and
{0,0,0,1}. All other values result in undefined behavior.
19.2.2.5 Platform Flash ECC Address Register (PFEAR)
The PFEAR is a 32-bit register for capturing the address of the last properly enabled ECC event in the
platform flash memory. Depending on the state of the ECC configuration register, an ECC event in the
platform flash causes the address, attributes and data associated with the access to be loaded into the
PFEAR, PFEMR, PFEAT, and PFEDR registers and also the appropriate flag (PF1BC or PFNCE) in the
ECC status register to be asserted.
This register is read-only; any attempted write is ignored. See Figure 19-5 and Table 19-7 for the platform
flash ECC address register definition.
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
19-9