PXN20RM Datasheet, PDF (532/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Enhanced Direct Memory Access Controller (eDMA)
Table 24-4. EDMA_ESR Field Descriptions (continued)
Field
SAE
SOE
DAE
DOE
NCE
SGE
SBE
DBE
Description
Source Address Error.
0 No source address configuration error.
1 The last recorded error was a configuration error detected in the TCD.SADDR field, indicating TCD.SADDR
is inconsistent with TCD.SSIZE.
Source Offset Error.
0 No source offset configuration error.
1 The last recorded error was a configuration error detected in the TCD.SOFF field, indicating TCD.SOFF is
inconsistent with TCD.SSIZE.
Destination Address Error.
0 No destination address configuration error.
1 The last recorded error was a configuration error detected in the TCD.DADDR field, indicating TCD.DADDR
is inconsistent with TCD.DSIZE.
Destination Offset Error.
0 No destination offset configuration error.
1 The last recorded error was a configuration error detected in the TCD.DOFF field, indicating TCD.DOFF is
inconsistent with TCD.DSIZE.
NBYTES/CITER Configuration Error.
0 No NBYTES/CITER configuration error.
1 The last recorded error was a configuration error detected in the TCD.NBYTES or TCD.CITER fields,
indicating the following conditions exist:
• TCD.NBYTES is not a multiple of TCD.SSIZE and TCD.DSIZE, or
• TCD.CITER is equal to zero, or
• TCD.CITER.E_LINK is not equal to TCD.BITER.E_LINK.
Scatter-Gather Configuration Error.
0 No scatter-gather configuration error.
1 The last recorded error was a configuration error detected in the TCD.DLAST_SGA field, indicating
TCD.DLAST_SGA is not on a 32-byte boundary. This field is checked at the beginning of a scatter-gather
operation after major loop completion if TCD.E_SG is enabled.
Source Bus Error.
0 No source bus error.
1 The last recorded error was a bus error on a source read.
Destination Bus Error.
0 No destination bus error.
1 The last recorded error was a bus error on a destination write.
24.3.2.3 eDMA Enable Request Register (EDMA_ERQRL)
The EDMA_ERQRL provides a bit map for the 32 channels to enable the request signal for each channel.
EDMA_ERQRL maps to channels 31–0.
The state of any given channel enable is directly affected by writes to this register; the state is also affected
by writes to the EDMA_SERQR and EDMA_CERQR. The EDMA_CERQR and EDMA_SERQR are
provided so that the request enable for a single channel can be modified without performing a
read-modify-write sequence to the EDMA_ERQRL.
24-12
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor