PXN20RM Datasheet, PDF (1100/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Analog-to-Digital Converter (ADC)
Address: ADC_BASE + 0x004C
Access: User read/write
0
R _DMA
W ⁹⁵
Reset 0
1
DMA
94
0
2
DMA
93
0
3
DMA
92
0
4
DMA
91
0
5
DMA
90
0
6
DMA
89
0
7
DMA
88
0
8
DMA
87
0
9
DMA
86
0
10
DMA
85
0
11
DMA
84
0
12
DMA
83
0
13
DMA
82
0
14
DMA
81
0
15
DMA
80
0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R _{DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA}
W ^{79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64}
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 34-17. DMA Channel Select Register 2 (DMAR2)
Table 34-17. DMAR2 Field Descriptions
Field
DMAn
Description
When set, channel n is enabled to transfer data in DMA mode.
34.3.2.17 Threshold Control Registers 0 – 3 (TRCn)
The four TRCn registers are used to store the user programmable upper thresholds’ values.
Address:
ADC_BASE + 0x0050 (TRC0)
ADC_BASE + 0x0054 (TRC1)
ADC_BASE + 0x0058 (TRC2)
ADC_BASE + 0x005C (TRC3)
Access: User read/write
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R _{THR THR THR} 0
0
0
0
0
0
W ^{EN INV OP}
THRCH
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 34-18. Threshold Control Registers 0 – 3 (TRCn)
Table 34-18. TRCn Field Descriptions
Field
THREN
THRINV
Description
Threshold enable.
When set, it enables the threshold detection feature for the selected channel.
Invert the output pin.
Setting this bit inverts the behavior of the threshold output pin.
34-20
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor