PXN20RM Datasheet, PDF (541/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Enhanced Direct Memory Access Controller (eDMA)
The contents of this register can also be polled and a non-zero value indicates the presence of a channel
error, regardless of the state of the EDMA_EEIR. The EDMA_ESR[VLD] bit is a logical OR of all bits in
this register and it provides a single bit indication of any errors. The state of any given channel’s error
indicators is affected by writes to this register; it is also affected by writes to the EDMA_CER. On writes
to EDMA_ERL, a 1 in any bit position clears the corresponding channel’s error status. A 0 in any bit
position has no effect on the corresponding channel’s current error status. The EDMA_CER is provided
so the error indicator for a single channel can be cleared.
Offset: EDMA_BASE + 0x002C
Access: User read-only
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R ERR ERR ERR ERR ERR ERR ERR ERR ERR ERR ERR ERR ERR ERR ERR ERR
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R ERR ERR ERR ERR ERR ERR ERR ERR ERR ERR ERR ERR ERR ERR ERR ERR
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 24-15. eDMA Error Register (EDMA_ERL)
Table 24-16. EDMA_ERL Field Descriptions
Field
ERRn
eDMA Error n.
0 An error in channel n has not occurred.
1 An error in channel n has occurred.
Description
24.3.2.15 DMA Hardware Request Status (EDMA_HRSL)
The EDMA_HRSL registers provide a bit map for the implemented channels (32) to show the current
hardware request status for each channel. EDMA_HRSL covers channels 31–00.
See Table 24-17 for the EDMA_HRSL definition.
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
24-21