PXN20RM Datasheet, PDF (618/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

FlexRay Communication Controller (FlexRAY)
NOTE
The controller does not provide a memory protection scheme for the
FlexRay memory.
26.1.5 Features
The controller provides the following features:
• FlexRay Communications System Protocol Specification, Version 2.1 Rev A compliant protocol
implementation
• FlexRay Communications System Electrical Physical Layer Specification, Version 2.1 Rev A
compliant bus driver interface
• Single channel support
— FlexRay Port A can be configured to be connected either to physical FlexRay channel A or
physical FlexRay channel B.
• FlexRay bus data rates of 10 Mbit/s, 8 Mbit/s, 5 Mbit/s, and 2.5 Mbit/s supported
• 128 configurable message buffers with
— Individual frame ID filtering
— Individual channel ID filtering
— Individual cycle counter filtering
• Message buffer header, status and payload data stored in dedicated FlexRay memory
— Allows for flexible and efficient message buffer implementation
— Consistent data access ensured by means of buffer locking scheme
— Application can lock multiple buffers at the same time
• Size of message buffer payload data section configurable from 0 to 254 bytes
• Two independent message buffer segments with configurable size of payload data section
— Each segment can contain message buffers assigned to the static segment and message buffers
assigned to the dynamic segment at the same time
• Zero padding for transmit message buffers in static segment
— Applied when the frame payload length exceeds the size of the message buffer data section
• Transmit message buffers configurable with state/event semantics
• Message buffers can be configured as
— Receive message buffer
— Single buffered transmit message buffer
— Double buffered transmit message buffer (combines two single buffered message buffer)
• Individual message buffer reconfiguration supported
— Means provided to safely disable individual message buffers
— Disabled message buffers can be reconfigured
• Two independent receive FIFOs
— One receive FIFO per channel
26-4
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor