PXN20RM Datasheet, PDF (483/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Software Watchdog Timer (SWT)
Offset: SWT_BASE + 0x0008
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
WTO
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
WTO
W
Reset 0
1
1
1
0
0
0
1
0
0
0
0
0
0
0
0
Figure 20-3. SWT Time-Out Register (SWT_TO)
Table 20-4. SWT_TO Register Field Descriptions
Field
Description
WTO Watchdog time-out period in clock cycles. An internal 32-bit down counter is loaded with this value or 0x0100,
whichever is greater, when the service sequence is written or when the SWT is enabled.
20.3.2.4 SWT Window Register (SWT_WN)
The SWT Window (SWT_WN) register contains the 32-bit window start value. This register is cleared on
reset. This register is read-only if either the SWT_CR[HLK] or SWT_CR[SLK] bits are set.
Offset: SWT_BASE + 0x000C
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
WST
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
WST
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 20-4. SWT Window Register (SWT_WN)
Table 20-5. SWT_WN Register Field Descriptions
Field
Description
WST Window start value. When window mode is enabled, the service sequence can only be written when the internal
down counter is less than this value.
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
20-5