PXN20RM Datasheet, PDF (1003/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Enhanced Serial Communication Interface (eSCI)
Offset: ESCI_BASE + 0x000A
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R RX
RDY
TX
RDY
L
WAKE
STO
PB
ERR
CERR
CK
ERR
FRC
0
0
0
0
0
0 UREQ OVFL
W w1c w1c w1c w1c w1c w1c w1c w1c
w1c w1c
Reset 0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 31-7. eSCI Interrupt Flag and Status Register 2 (eSCI_IFSR2)
Table 31-8. LINSTAT1 Field Descriptions
Field
RXRDY
TXRDY
LWAKE
STO
PBERR
CERR
CKERR
FRC
UREQ
OVFL
Description
Receive Data Ready Interrupt Flag. This interrupt flag is set when the payload data of a received frame is
transferred into the LIN Receive Register (eSCI_LRR).
Transmit Data Ready Interrupt Flag. This interrupt flag is set when the content of the LIN Transmit Register
(eSCI_LTR) is processed by the LIN PE either to generate a frame header or to transmit frame data.
LIN Wakeup Received Flag. This interrupt flag is set when a LIN wakeup character is received, as described in
Section 31.4.6.6, LIN Wakeup.
Slave Timeout Interrupt Flag. This interrupt flag is set when a Slave-Not-Responding-Error is detected. A
detailed description is given in Section 31.4.6.5.5, Slave-Not-Responding-Error Detection.
Physical Bus Error Flag. This interrupt flag is set when the receiver input remains unchanged for at least 31
RCLK clock cycles after the start of a byte transmission, as described in Section 31.4.6.5, LIN Error Reporting.
CRC Error Flag. This interrupt flag is set when an incorrect CRC pattern was detected for a received LIN frame.
Checksum Error Flag. This interrupt flag is set when a checksum error was detected for a received LIN frame.
Frame Complete Flag. This interrupt flag is set when a LIN frame was completely transmitted or received.
Unrequested Data Received Flag. This interrupt flag is set when unrequested activity has been detected on the
LIN bus, as described in Section 31.4.6.5, LIN Error Reporting.
Overflow Flag. This interrupt flag is set when an overflow as described in Section 31.4.6.5.8, Overflow Detection,
was detected.
31.3.2.7 eSCI LIN Control Register 1 (eSCI_LCR1)
This register provides control bits to control and configure the LIN hardware. This register provides the
interrupt enable bits for the interrupt flags in Interrupt Flag and Status Register 2 (eSCI_IFSR2).
Offset: ESCI_BASE + 0x000C
Access: User read/write
0
1
R
LRES WU
W
Reset 0
0
2
3
4
5
6
7
8
9
10
11
12
13
14
15
WUD
0
0
PRTY LIN RXIE TXIE WUIE STIE PBIE CIE CKIE FCIE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 31-8. eSCI LIN Control Register 1 (eSCI_LCR1)
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
31-13