PXN20RM Datasheet, PDF (475/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Error Correction Status Module (ECSM)
Offset: ECSM_BASE_ADDR + 0x0066
Access: User read-only
0
1
2
3
4
5
6
7
R
0
0
0
0
PREMR
W
Reset
0
0
0
0
U
U
U
U
Figure 19-12. Platform RAM ECC Master Number (PREMR) Register
Table 19-14. PREMR Field Descriptions
Field
Description
PREMR Platform RAM ECC Master Number Register. Contains the AXBS bus master number of the faulting access of the
last properly enabled platform RAM ECC event.
19.2.2.12 Platform RAM ECC Attributes Register (PREAT)
The PREAT is an 8-bit register for capturing the AXBS bus master attributes of the last properly enabled
ECC event in the platform RAM memory. Depending on the state of the ECC configuration register, an
ECC event in the platform RAM causes the address, attributes, and data associated with the access to be
loaded into the PREAR, PRESR, PREMR, PREAT, and PREDR registers and also the appropriate flag
(PR1BC or PRNCE) in the ECC status register to be asserted.
This register is read-only; any attempted write is ignored. See Figure 19-13 and Table 19-15 for the
platform RAM ECC attributes register definition.
Offset: ECSM_BASE_ADDR + 0x0067
Access: User read-only
0
1
2
3
4
5
6
7
R WRITE
SIZE
PROTECTION
W
Reset
U
U
U
U
U
U
U
U
Figure 19-13. Platform RAM ECC Attributes (PREAT) Register
Table 19-15. PREAT Field Descriptions
Field
WRITE 0 Read access.
1 Write access.
Description
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
19-15