PXN20RM Datasheet, PDF (1246/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Nexus Development Interface (NDI)
NOTE
Set the OVC bits within the DC1 register to delay the CPU to alleviate (but
not eliminate) potential overrun situations.
Error information is messaged out in the following format (see Table 36-47)
:
3
2
1
ECODE (00110 / 01000)
SRC
TCODE (001000)
MSB
5 bits
4 bits
6 bits LSB
Fixed length = 15 bits
Figure 36-77. Error Message Format
36.7.9.4.4 Watchpoint Timing Diagram (2 MDO/1 MSEO Configuration)
MCKO
Watchpoint
Error
MSEO
MDO[1:0]
11 11 00 00 10 00 00 00 10 00 00 10 01 00
WPM:
TCODE = 15
Source Processor = 0b00
Watchpoint Number = 2
Error:
TCODE = 8
Source Processor = 0b00
Error Code = 6 (Queue Overrun – WPM Only)
Note: This is representative only. The PXN20 supports only Full-Port Mode with 12 MDO pins.
Figure 36-78. Watchpoint Message and Watchpoint Error Message
36.7.9.5 Nexus2+ Read/Write Access to Memory-Mapped Resources
The read/write access feature allows access to memory-mapped resources via the JTAG/OnCE port. The
read/write mechanism supports single as well as block reads and writes to e200z0 system bus resources.
The Nexus2+ module is capable of accessing resources on the e200z0 system bus, with multiple
configurable priority levels. Memory-mapped registers and other non-cached memory can be accessed via
the standard memory map settings.
All accesses are setup and initiated by the read/write access control/status register (RWCS), as well as the
read/write access address (RWA) and read/write access data registers (RWD).
Using the read/write access registers (RWCS/RWA/RWD), memory-mapped e200z0 system bus resources
can be accessed through Nexus2+. The following subsections describe the steps required to access
memory-mapped resources.
NOTE
Read/write access can only access memory mapped resources when system
reset is de-asserted.
36-96
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor