PXN20RM Datasheet, PDF (464/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Error Correction Status Module (ECSM)
Offset: ECSM_BASE_ADDR + 0x0024
0
1
2
3
4
R FXS FXS FXS FXS 0
W ^{BE0 BE1 BE2 BE3}
Reset 0
0
0
0
0
5
6
7
8
9
10
11
0 FXS FXS RBEN WBEN ACC 0
BE6 BE7
ERR
0
0
0
0
0
0
0
Access: User read/write
12
13
14
15
0
0
0
0
0
0
0
0
16
R0
W
Reset 0
Field
FXSBEn
[0:7]
RBEN
WBEN
ACCERR
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 19-1. FEC Burst Optimization Master Control Register (FBOMCR)
Table 19-3. FBOMCR Field Descriptions
Description
FEC XBAR slave burst enable. FXSBEn enables bursting by the FEC interface to the XBAR slave port
controlled by that respective FXSBEn bit. If FXSBEn is asserted, then that XBAR slave port enabled by
the bit can accept the bursts allowed by RBEN and WBEN. Otherwise, the FEC interface will not burst to
the XBAR slave port controlled by that respective FXSBEn bit. Read bursts from that XBAR slave port are
enabled by RBEN. Write bursts to that XBAR slave port are enabled by WBEN.
FXSBE0 = Burst enable for haddr[31:29] = 3'h0
FXSBE1 = Burst enable for haddr[31:29] = 3'h1
FXSBE2 = Burst enable for haddr[31:29] = 3'h2
FXSBE3 = Burst enable for haddr[31:29] = 3'h3
FXSBE4 = Burst enable for haddr[31:29] = 3'h4
FXSBE5 = Burst enable for haddr[31:29] = 3'h5
FXSBE6 = Burst enable for haddr[31:29] = 3'h6
FXSBE7 = Burst enable for haddr[31:29] = 3'h7
Global read burst enable from XBAR slave port designated by FXSBEn
0 Read bursting from all XBAR slave ports is disabled.
1 Read bursting is enabled from any XBAR slave port whose FXSBEn bit is asserted.
Global write burst enable to XBAR slave port designated by FXSBEn
0 Write bursting to all XBAR slave ports is disabled.
1 Write bursting is enabled to any XBAR slave port whose FXSBEn bit is asserted.
Accumulate error - This bit determines whether an error response for the first half of the write burst is
accumulated to the second half of the write burst or discarded. In order to complete the burst, the FEC
interface to the system bus responds by indicating that the first half of the burst completed without error
before it actually writes the data so that it can fetch the second half of the write data from the FIFO. When
actually written onto the system bus, the first half of the write burst can have an error. Because this half
initially responded without an error to the FIFO, the error is discarded or accumulated with the error
response for the second half of the burst.
0 Any error to the first half of the write burst is discarded.
1 Any actual error response to the first half of the write burst is accumulated in the second half's response.
In other words, an error response to the first half will be seen in the response to the second half, even
if the second half does not error.
19-4
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor