PXN20RM Datasheet, PDF (183/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Chapter 8
System Integration Unit (SIU)
8.1 Introduction
The system integration unit (SIU) controls MCU reset configuration, the system reset operation, pad
configuration, external interrupt, general purpose I/O (GPIO), internal peripheral multiplexing, clock
frequency divider configuration, peripheral clock disable configuration, and peripheral clock disable
acknowledge. The reset configuration block contains the external pin boot configuration logic. The pad
configuration block controls the static electrical characteristics of I/O pins. The GPIO block provides
uniform and discrete input/output control of the MCU I/O pins. The reset controller performs reset
monitoring of internal and external reset sources, and drives the RESET pin. The core accesses the SIU
through the peripheral bus.
8.1.1 Block Diagram
Figure 8-1 is a block diagram of the SIU. The signals shown are external pins to the device. The SIU
registers are accessed through the crossbar switch. The power-on reset (POR) detection block, pad
interface/pad ring block, and peripheral I/O channels are external to the SIU.
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor
8-1