PXN20RM Datasheet, PDF (762/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

FlexRay Communication Controller (FlexRAY)
26.6.19.4 Freeze after System Bus Failure
If the SBFF bit in the Module Configuration Register (MCR) is set to 1, the controller will go into the
freeze mode immediately after the occurrence of one of the system bus access failures.
26.6.20 Interrupt Support
The controller provides 172 individual interrupt sources and five combined interrupt sources.
26.6.20.1 Individual Interrupt Sources
26.6.20.1.1 Message Buffer Interrupts
The controller provides 128 message buffer interrupt sources.
Each individual message buffer provides an interrupt flag MBCCSRn[MBIF] and an interrupt enable bit
MBCCSRn[MBIE]. The controller sets the interrupt flag when the slot status of the message buffer was
updated. If the interrupt enable bit is asserted, an interrupt request is generated.
26.6.20.1.2 FIFO Interrupts
The controller provides 2 FIFO interrupt sources.
Each of the 2 FIFO provides a Receive FIFO Almost Full Interrupt Flag. The controller sets the Receive
FIFO Almost Full Interrupt Flags (GIFER.FAFBIF, GIFER.FAFAIF) in the Global Interrupt Flag and
Enable Register (GIFER) if the corresponding Receive FIFO fill level exceeds the defined watermark.
26.6.20.1.3 Wakeup Interrupt
The controller provides one interrupt source related to the wakeup.
The controller sets the Wakeup Interrupt Flag GIFER.WUPIF when it has received a wakeup symbol on
the FlexRay bus. The controller generates an interrupt request if the interrupt enable bit GIFER.WUPIE is
asserted.
26.6.20.1.4 Protocol Interrupts
The controller provides 25 interrupt sources for protocol related events. For details, see Protocol Interrupt
Flag Register 0 (PIFR0) and Protocol Interrupt Flag Register 1 (PIFR1). Each interrupt source has its own
interrupt enable bit.
26.6.20.1.5 CHI Error Interrupts
The controller provides 16 interrupt sources for CHI related error events. For details, see CHI Error Flag
Register (CHIERFR). There is one common interrupt enable bit GIFER.CHIIE for all CHI error interrupt
sources.
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PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor